NDLI: Sixth Annual IEEE International ASIC Conference and Exhibit

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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

EtherCore application specific standard products

Large system asynchronous design

Programmable capabilities allow field customization of ASIC devices

An ASIC signal processor for electronic warfare receivers

Microprogram sequencer with concurrent error detection

Modelling of a self timed dataflow processor in VHDL

A CMOS phase detector for mixed signal ASIC application

Motorola MC68040 high-speed design using altera EPM5000 erasable programmable logic devices

RLRAM: A VLSI implementation of a resetable, loadable RAM module

A CMOS circuit technique for high-speed RAMs

A 2K /spl times/ 8-bit single-chip digital radio frequency memory

Accelerated fuzzy pattern classification with ASICs

Top down system design using VHDL [FFT system]

A top down design environment for data-path design [FIR filter]

Parameter-driven data path VHDL model generation for ASIC design

Improving FSMD design assurance

Modeling for synthesis in VHDL

System level verification of ASIC chip-sets

Implementing a timing shell for VHDL simulation using the proposed EIA-567 standard

ASIC system design considerations

Experiences with an HDL-based design method for complex architectures

A design consultant to support CAD tool usage

A full custom VLSI design methodology using Mentor Graphics design software in an educational environs

ASIC manufacturability simulation

Technology issues of library porting in multi-process environment

An automatic cell characterization environment for cell-based design methodology

A multi-FPGA prototype of a DS1/HDSL synchronizer and desynchronizer prior to ASIC fabrication

FPGA architectures for ASIC hardware emulators

Walsh function generator using a field programmable gate array [for ESTAR]

A FPGA ASIC communication channel systems emulator

Implementing a fuzzy inference engine using FPGA

A 155.52 Mb/s receiver chip architecture and its simulation methodology for SONET OC-3 application

XBERT - A versatile 622 Mb/sec bit error rate generator/receiver methodology for SONET OC-3 application

A clock/data extraction device for use in ATM electro-optical networks

Study of a SONET STS-3c based ATM user network interface design

A 531 Mb/s fibre channel SIPO/PISO chip set capable of driving 50 m of shielded twisted pair

An extended hyperbolic hop code transmitter

A semicustom implemented connection matrix for SDH systems

A 5 Mbit/sec data transceiver chip for the 'FIP' protocol

Implementation and performance of GaAs digital signal processing ASICs

Pipeline scheduling techniques in high-level synthesis

Development of neural network tools for ASIC design

High-level DSP synthesis using the COMET design system

A synthesis tool based design of a 111 MHz CMOS floating point adder with built in testability

A cell-based datapath synthesizer for ASICs

An architecture synthesis of low-level communication circuits

Interconnect optimization in behavioral synthesis of ASICs

Decomposition of logic functions with partial vertex chart

ECL I/O buffers for BiCMOS integrated systems: A tutorial overview

CMOS I/O transceiver with 3V/5V level converter and N-tub voltage generator

Three volt to five volt CMOS interface circuit device leakage limited DC power dissipation

Current mode transceiver logic, (CMTL) for reduced swing CMOS, chip to chip communication

Digital transistor sizing techniques applied to 100K ECL CMOS output buffers

An adaptive CMOS transmission line driver

Performance evaluation of MCM chip-to-chip interconnections using custom I/O buffer designs

Design of a high speed interface for 0.5/spl mu/m gate arrays

Design and fabrication of long wavelength OEICs

Monolithic PIN-FET photoreceivers

Parallel optical interconnects for Scalable Coherent Interface

MMIC front-ends for optical communication systems

High speed and high performance long wavelength OEICs using heterojunction bipolar transistors

Time domain optimisation of high bit rate optical receivers

Linear IC parasitic element simulation methodology

Interconnect and output driver modeling of high speed designs

New delay model for 0.5/spl mu/ CMOS ASIC

Application of process statistics to macro/behavioral modeling

A processor interface model for fast system simulations

Simulation techniques for systems with oversampling A/D converters

A mixed analog-digital simulator for ASIC using a novel block tearing approach

CircuitSim93: A circuit simulator benchmarking methodology case study

A transistor voltage reference-and what the bandgap has to do with it

Two gallium-arsenide second-order sigma-delta modulators for 8 MHz bandwidths

An ASIC mixed-mode analog front end

A baseband mixed signal ASIC for CDMA subscriber equipment applications

A wideband, fixed gain BiMOS amplifier

"Piecewise-quadratic" synthesis of an exponential characteristic with an array of square-law MOSFETs

Test tradeoffs in ASIC design: tutorial

ASIC DFT techniques and benefits

A specification driven hierarchical test methodology

Testable design environment with test-added tools

Automated test data development for semi-custom ICs: An ideal approach to fast development

Direct comparison of 2 set of results from testability analysis by using correlation and statistical testability analysis of transient (delay) faults

Automatic fault model/logic model generation for large scale ASIC circuits

Physical design tradeoffs for ASIC technologies

Zero skew clock routing algorithm for high performance ASIC systems

Process-variation-tolerant zero skew clock routing

Closing the gap: Near-optimal Steiner trees in polynomial time

Placement and placement driven technology mapping for FPGA synthesis

An asymptotically optimal algorithm for gate array placement

ECHO2, a multi-channel, single-chip, VLSI ECHO canceller with embedded TMS320C10 DSP

Adaptive thresholding ASIC for image processing application

A bit-serial realization of a lattice wave digital intermediate frequency filter for mobile radio systems

Proven-prompt vector normalizer

SEARCH1: A multiprocessor chip for disk drive applications

Development of high performance ASICs using ACUITY image resizing engine cores

Tutorial on design for testability (DFT) "An ASIC design philosophy for testability from chips to systems"

Design verification techniques for system level testing using ASIC level BIST implementations

Analysis of the gap between behavioral and gate level fault simulation

Circuit partitioning for pseudo-exhaustive test

Comparison of voltage and current testing of analogue and mixed-signal circuits

A highly portable, self-stimulating and self-testing reliability test chip for ASIC products

Testability of ECL circuits in a BiCMOS process

5-volt to 3-volt evolution paths: Selecting a gate array product for the next generation

BiNMOS-CBA: An optimum solution for high performance EDP and telecom applications

A sub-50 psec. 89 K gate ECL-gate array with 480 Kb BiCMOS STRAM

1V high-speed digital circuit technology with 0.5/spl mu/m multi-threshold CMOS

A datapath compiler library for 0.7/spl mu/m CMOS

A 100% body utilization ROM/PLA compiler design for sea-of-gate

An ECL gate array with 2.5 GHz embedded PLL

Timing- and thermal-oriented placement for multi-chip modules

A model for verification of coupled high-speed packages and interconnects

A floorplanning system for tape automated bonding packages

Timing skew of the equal-length serpentines routing

Net ordering for timing and wiring optimization

VLSI neural network architectures

Data compression and VLSI implementation neuroprocessor

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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