NDLI: Behavioral fault simulation and ATPG, system for VHDL

Content Provider	IEEE Xplore Digital Library
Author	Noh, T.H. Chen, C.-I.H. Chung, S.M.
Copyright Year	1994
Description	Author affiliation: Defence Electron Supply Center, ELDC/Custom Microelectron., Dayton, OH, USA (Noh, T.H.)
Abstract	Due to the increasing level of integration achieved by Very Large Scale Integrated (VLSI) technology, traditional gate-level fault simulation becomes more complex, difficult, and costly. Behavioral fault simulation at top functional level, described in a hardware description language, offers very attractive alternatives to these problems. This paper presents a new way to simulate the behavioral fault models for the Very high speed integrated circuits Hardware Description Language (VHDL). The performance analysis shows that relatively small number of test patterns generated by the behavioral fault simulation and Automatic Test Pattern Generation (ATPG) system detects around 98 percent of all testable gate-level faults.<>
Starting Page	412
Ending Page	416
File Size	501833
Page Count	5
File Format	PDF
ISBN	0780320204
DOI	10.1109/ASIC.1994.404531
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit faults Circuit simulation Very large scale integration Hardware design languages Integrated circuit technology Integrated circuit modeling Very high speed integrated circuits Performance analysis Test pattern generators
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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