NDLI: ASIC packaging directions

Please wait, while we are loading the content...

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit

Proceedings of Eighth International Application Specific Integrated Circuits Conference

Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit

Sixth Annual IEEE International ASIC Conference and Exhibit

[1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit

A fuzzy neural network chip based on systolic array architecture

An analysis and design of an optimal programmable analog CMOS synapse

Digitally programmable continuous-time lowpass filter for tape drives

ASIC packaging directions

An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone

An analog parallel processor for the dynamic programming paradigm

A VLSI-chip for a hardware-accelerator for the simplex-method

The COREWARE methodology: building a 200 MFLOP processor in 9 man months

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

An ASIC architecture for implementing low-level communication circuits

Automatic error pattern generation for design error detection in a design validation simulation system

Behavioural VHDL code generation for synchronous FSMs

Concurrent design of a chipset and its runtime environment

The design of a competitive ASIC for the consumer market using the PIRAMID design system

Robin Hood: a system timing verifier for multi-phase level-sensitive clock designs

A low-voltage metal-programmable SRAM compiler for gate array

Ramgen: a dual port static RAM generator

A high speed metal programmable static RAM compiler for 0.7 mu m CMOS gate array

A parallel BDD engine for logic verification

An efficient MOS VLSI timing simulator on parallel computers

MATEG: a hierarchical test generator for module-based circuits

A methodology for automated behavioral verification of floating-point designs

A minimal hardware overhead BIST data compaction scheme

A simulation based strategy for mixed-signal testing

Transient response testing of mixed-signal ASICs

Fault diagnosis of analog circuits using artificial neural networks as signature analyzers

Testing gate-to-channel shorts in BiCMOS logic gates

Using high level design models for generation of test vectors

An 8*8 discrete cosine transform model using VHDL

Automatic logic and timing model generation for cell based design

Improved modelling and characterization system for logic simulation

Accurate VHDL libraries for ASIC design

Using VHDL for modeling and design of processing units

VLSI design of a neural processing element for the Boltzmann machine

Design of a 50 MFIPS fuzzy controller ASIC

Micro data flow

Asynchronous design techniques

On-chip terminating resistors for high speed ECL-CMOS interfaces

Comparison of CMOS and BiCMOS performance on digital cells-a case study: the bit slice processor 2901

A tutorial on GaAs vs silicon

The design approach to ASICs in education

Teaching ASIC design with FPGAs

Fast turn-around ASIC design environment with design assistant tools

Use of VHDL synthesis in an advanced digital design course

Automating circuit simulation and evaluation for the semi-custom IC design process

Evaluating VHDL-based ASIC synthesis tools

Pre-design consideration and evaluation for ASICs

BAT: an ASIC I/O interface analysis and synthesis tool

Ground bounce, what you simulate may not be what you get

3-D interconnect capacitance calculation for multi-conductor and its application to a ROM circuit design

Advanced delay analysis method for submicron ASIC technology

Transmission line models of multi-chip module interconnects

3 volt ASIC macrocells for PC and controller applications

Low voltage standard (for logic design)

Integrating a full custom microprocessor in a user defined ASIC array as a fully diffused core

16 Kbit BiCMOS compilable gate array RAM with 2.5 ns access time

A 473 K gate 0.7 mu CMOS gate array

A 0.65 mu m, low-voltage/low-power optimized CMOS gate array

A 5 volt 0.5 mu m mixed BiCMOS/CMOS channelless gate array

A 1.2 mu m CMOS differential I/O system capable of 400 Mbps transmission rates

VLSI focal-plane array processor for morphological image processing

Analog neural network circuits for ASIC fabrication

A video ADC macro for A&D mixed cell-based IC

Designing programmable hearing aids using BiCMOS

On the implementation of switched capacitor circuits in gate arrays

A universal single chip analog CMOS speech processor for analog mobile cellular phones

An 8-10-bit, 1-40 MHz analog signal processor with configurable performance for electronic imaging applications

Embedded 6 bit flash converter design for digital stereo sound decoder

Distributed automatic test pattern generation

Results of a topologically partitioned parallel automatic test pattern generation system on a distributed-memory multiprocessor

The use of bit conserving logic in design for testability

Scan cell design for enhanced delay fault testability

A fully integrated characterization and management system for ASIC libraries

Four layer metal, flip chip, submicron ASIC product designed for advanced multichip module

Evaluation of test strategies for multichip modules

High-performance microelectronic substrate verification using probe testers

Multilayer routing algorithm for high performance MCMs

Electrical performance analysis of packaged CMOS ASIC devices and systems

Technology and interconnect simulation for high-speed multi-chip modules

Strategies for implementation independent DSP system development using HDL based design automation

High performance DSP ASIC for multiply, divide and square root

Development and simulation of a 4080-point Winograd fast Fourier transform processor

A video image processor for real-time centroid calculation

Image processing ASIC for real-time contrast enhancement

An edge detection ASIC for real time defect detection

A JBIG arithmetic coder-decoder chip

Silicon assembler design of a DCT/IDCT ASIC for real-time JPEG/MPEG compression

A serial/parallel color matrix, 2D convolution and 9-Tap filter ASIC with a systems perspective

Synthesized self-timed synchronous systems

A synthesis system for communication protocols

Memory management for high level synthesis applications

Grouping variables into multiport memories for ASIC data path synthesis

An incremental synthesis method for ASIC design

Automatic VHDL synthesizability checking based on the user-defined rules for ASIC design

Synthesis: its evolution and what you can do with it today

Comprehensive structural testing of ASIC macrocells, a comparative analysis

Tutorial on design for testability

Testability measure and analysis

A standard cell set for delay insensitive VLSI design

Resonator based digital filters using field programmable gate array elements

FFT processor using field programmable gate arrays

Amorphous silicon anti-fuse for high-speed FPGA application

An optimised FPGA configuration for signal processing

ASIC technologies

An ETL gate array implementation of a 2.5 Gb/s, 48-bit wide, channel programmable demultiplexer for fiber optic data transmission

VLSI CMOS implementation of the shuffleout ATM switch interconnection matrix

4B5B decoder for FDDI

Bus driver IC for use in vehicle multiplexing communications

An approach to data security in today's networked environment

ASIC implementation of a 16-kbps waveform coder using adaptive vector quantization

A CMOS ASIC for real time microwave spectral estimation applications

Monolithic GPS receiver and synthesizer using high-speed silicon bipolar technology

A GaAs ASIC chip set for NASAs deep space network

Early wirability checking and 2D congestion-driven circuit placement

A circuit component placer for optimizing layout with arbitrarily shaped rectilinear and soft blocks

Improving the quadratic objective function in module placement

Layout synthesis of combinational blocks from behavioral hardware descriptions

Physical synthesis for performance optimization

Timing driven placement of pads and latches

An implementation of a clock-tree distribution scheme for high-performance ASICs

Minimum skew multiple clock routing in synchronous ASIC systems

Zero-skew clock routing trees with minimum wirelength

Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4)

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in