NDLI: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing

Content Provider	IEEE Xplore Digital Library
Author	Dutta, H. Hannig, F. Teich, J. Heigl, B. Hornegger, H.
Copyright Year	2006
Description	Author affiliation: Siemens AG, Medical Solutions (AX), Forchheim, Germany. (Heigl, B.; Hornegger, H.) \|\| University of Erlangen-Nuremberg, Germany (Dutta, H.; Hannig, F.; Teich, J.)
Abstract	Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper, we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. The final architecture deliver similar synthesis results as a hand-tuned design.
Starting Page	331
Ending Page	340
File Size	605125
Page Count	10
File Format	PDF
ISBN	0769526829
ISSN	21600511
DOI	10.1109/ASAP.2006.4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Hardware Acceleration Adaptive filters Image processing Signal processing algorithms Biomedical imaging Field programmable gate arrays Medical diagnostic imaging Application software
Content Type	Text
Resource Type	Article

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A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing