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  1. Volume Year : 1994 Num : 43
  2. Issue 11
  3. Comparative fault tolerance of parallel distributed processing networks
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Issue 11
A parallel virtual machine for programs composed of abstract data types
The size of reduced OBDD's and optimal read-once branching programs for almost all Boolean functions
A new routing algorithm for a class of rearrangeable networks
Performance modelling and comparisons of global shared buffer management policies in a cluster environment
On polynomial-time testable combinational circuits
Serial array time slot interchangers and optical implementations
New self-routing permutation networks
Comparative fault tolerance of parallel distributed processing networks
Fuzzy systems as universal approximators
Optimal centralized algorithms for store-and-forward deadlock avoidance
A unified and division-free CORDIC argument reduction method with unlimited convergence domain including inverse hyperbolic functions

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Comparative fault tolerance of parallel distributed processing networks

Content Provider IEEE Xplore Digital Library
Author Segee, B.E. Carter, M.J.
Copyright Year 1968
Abstract We propose a method for evaluating and comparing the fault tolerance of a wide variety of parallel distributed processing networks (more commonly referred to as artificial neural networks). Despite the fact that these computing networks are biologically inspired and share many features of biological neural networks, they are not inherently tolerant of the loss of processing elements. We examine two classes of networks, multilayer perceptrons and Gaussian radial basis function networks, and show that there is a marked difference in their operational fault tolerance. Furthermore, we show that fault tolerance is influenced by the training algorithm used and even the initial state of the network. Using an idea due to Sequin and Clay (1990), we show that training with intermittent, randomly selected faults can dramatically enhance the fault tolerance of radial basis function networks, while it yields only marginal improvement when used with multilayer perceptrons.<>
Sponsorship IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page 1323
Ending Page 1329
Page Count 7
File Size 808945
File Format PDF
ISSN 00189340
Volume Number 43
Issue Number 11
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 1994-11-01
Publisher Place U.S.A.
Access Restriction One Nation One Subscription (ONOS)
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Fault tolerance Distributed processing Routing Delay effects Very large scale integration Hardware Computer networks Parallel processing Clocks Communication switching
Content Type Text
Resource Type Article
Subject Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture
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