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  1. IEEE Solid-State Circuits Magazine
  2. Year : 2009 Volume : 1
  3. Issue 3
  4. Searching for the dream embedded memory
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Year : 2016 Volume : 8
Year : 2015 Volume : 7
Year : 2014 Volume : 6
Year : 2013 Volume : 5
Year : 2012 Volume : 4
Year : 2011 Volume : 3
Year : 2010 Volume : 2
Year : 2009 Volume : 1
Issue 4
Issue 3
Table of contents
Contributors
Conferences in crisis [President's corner]
Listen up! IEEE online conferences [from the Executive Director]
Tsinghua-Cradle of engineers, entrepreneurs, and statesmen [Associate editors' view]
ARM gets serious about IP (Second in a two-part series [Associated Editors' View]
How TI adopted VLIW in digital signal processors
How VLIW almost disappeared - and then proliferated
Design for manufacturability for fabless manufactuers
Searching for the dream embedded memory
Chapters
Ballot watch [Society news]
CEDA currents [IEEE News]
Conference Reports
Calendar
Highlights from ISSCC 2009 [Footer]
Issue 2
Issue 1

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Searching for the dream embedded memory

Content Provider IEEE Xplore Digital Library
Author Natarajan, S. Chung, S. Paris, L. Keshavarzi, A.
Copyright Year 2009
Abstract In this paper, it was concluded that embedding memories into an SOC increases bandwidth, speed, and reliability of the overall system, while reducing power consumption and form factor. Embedded DRAM is an attractive choice for embedded memory because it consumes only 30% of standby power and 10% of active power, while it occupies only 30% of the area, compared to SRAM at the 90-nm CMOS node. At the same level of technology, embedded DRAM can achieve a soft-error rate of less than 1 FIT per Mb, which is ten to 1,000 times smaller than that of a comparable SRAM. However, a careful assessment of the benefits must be weighed against the increased process cost of four to six extra masks and masking operations. Emerging memories such as MRAM and PCRAM are nonvolatile with almost unlimited endurance and offer five orders of magnitude faster write speed than flash memory does, yet with read speed close to that of embedded DRAM. In addition, they are potentially simpler to fabricate. The MRAM cell is based on a multilayer magnetic tunnel junction with a parallel or antiparallel state to provide a 0 or1 logic state. The PCRAM cell is based on a reversible phase change between crystalline and amorphous states to provide a 0 or 1 state. These mechanisms have been proven in magnetic heads in hard disk drives and in readable/writable DVDs in discrete form. They are suitable for use as level-two or level-three cache or main memory or as storage devices for code or data. These emerging memories are about ready to be integrated into mainstream CMOS semiconductor processes.
File Size 2602676
File Format PDF
ISSN 19430582
Volume Number 1
Issue Number 3
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2009-01-01
Publisher Place U.S.A.
Access Restriction One Nation One Subscription (ONOS)
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Random access memory Phase change random access memory Power system reliability Bandwidth Energy consumption CMOS technology Costs Read-write memory Nonvolatile memory Flash memory
Content Type Text
Resource Type Article
Subject Electrical and Electronic Engineering
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