NDLI: High-speed /spl Sigma//spl Delta/ modulators with reduced timing jitter sensitivity

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High-speed /spl Sigma//spl Delta/ modulators with reduced timing jitter sensitivity

Content Provider	IEEE Xplore Digital Library
Author	Luschas, S. Hae-Seung Lee
Copyright Year	1992
Abstract	As higher and higher frequency signals are sampled, clock jitter limits the achievable signal-to-noise ratio (SNR) in an analog-to-digital converter (ADC). This clock jitter limit is reviewed for upfront sampled ADCs and continuous-time (CT) sigma-delta modulators (/spl Sigma//spl Delta/Ms). A pulse-shaped feedback digital-to-analog converter (DAC) is proposed to mitigate the jitter-imposed SNR limit in CT /spl Sigma//spl Delta/Ms. An intuitive analysis that compares the pulse-shaped DAC to conventional DACs is presented. This analysis as well as a more rigorous analysis shows that the pulse-shaped feedback /spl Sigma//spl Delta/M has potential for significant SNR improvement over conventional CT /spl Sigma//spl Delta/Ms as well as any upfront sampled system. For typical jitter, phase and amplitude noise numbers, SNR improvement is on the order of 17 dB over a conventional CT /spl Sigma//spl Delta/M and 8 dB over an upfront sampled ADC for a 1-GHz input.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	712
Ending Page	720
Page Count	9
File Size	535171
File Format	PDF
ISSN	10577130
Volume Number	49
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing jitter Signal to noise ratio Clocks Feedback Frequency conversion Analog-digital conversion Delta-sigma modulation Digital-analog conversion Noise level Phase noise
Content Type	Text
Resource Type	Article

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