NDLI: Gigahertz logic gates based on InP-MISFET's with minimal drain current drift

Content Provider	IEEE Xplore Digital Library
Author	Pande, K.P. Fathimulla, M.A. Gutierrez, D. Messick, L.
Copyright Year	1980
Abstract	Three-input AND/NOR logic gates based on 3-µm overlapping gate InP-MISFET technology were fabricated and clocked at 1 GHz. The logic gates showed a propagation delay of ∼500-700 pS/gate for a channel length of 1.5 µm. Such high-speed performance was obtainable as a result of a novel process that was used in the fabrication of the MISFET's. The process included the saturation of InP surface with phosphorus vapor and growth of a P2OxN1-xinterfacial layer followed by the deposition of an SiO2gate insulator. MISFET's that were utilized in the logic gates showed a channel mobility of ∼3700 cm²/V.s and less than 3-percent drain current drift.
Sponsorship	IEEE Electron Devices Society
Starting Page	407
Ending Page	409
Page Count	3
File Size	335034
File Format	PDF
ISSN	07413106
Volume Number	7
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-07-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Indium phosphide Dielectric substrates Fabrication Circuits Annealing Metallization Logic devices Sea surface Plasma immersion ion implantation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Electronic, Optical and Magnetic Materials

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Gigahertz logic gates based on InP-MISFET's with minimal drain current drift