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  1. Transactions on Design Automation of Electronic Systems (TODAES)
  2. ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
  3. Issue 3, August 2007
  4. Binary synthesis
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ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 22
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 21
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 20
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 19
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 18
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 17
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 16
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 15
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 14
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 13
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 12
Issue 4, September 2007
Issue 3, August 2007
Introduction to special issue on demonstrable software systems and hardware platforms
Efficient simulation of critical synchronous dataflow graphs
A framework for heterogeneous specification and design of electronic embedded systems in SystemC
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches
PeaCE: A hardware-software codesign environment for multimedia embedded systems
Efficient power modeling and software thermal sensing for runtime temperature monitoring
HW-SW emulation framework for temperature-aware design in MPSoCs
Efficient and scalable compiler-directed energy optimization for realtime applications
Circuit-simulated obstacle-aware Steiner routing
Probabilistic system-on-a-chip architectures
A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current
A verification system for transient response of analog circuits
Postplacement rewiring by exhaustive search for functional symmetries
EWD: A metamodeling driven customizable multi-MoC system modeling framework
Binary synthesis
Speedups in embedded systems with a high-performance coprocessor datapath
Event propagation for accurate circuit delay calculation using SAT
Issue 2, April 2007
Issue 1, January 2007
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 11
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 10
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 9
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 8
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 7
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 6
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 5
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 4
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 3
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 2
ACM Transactions on Design Automation of Electronic Systems (TODAES) : Volume 1

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Binary synthesis

Content Provider ACM Digital Library
Author Vahid, Frank Stitt, Greg
Copyright Year 2008
Abstract Recent high-level synthesis approaches and C-based hardware description languages attempt to improve the hardware design process by allowing developers to capture desired hardware functionality in a well-known high-level source language. However, these approaches have yet to achieve wide commercial success due in part to the difficulty of incorporating such approaches into software tool flows. The requirement of using a specific language, compiler, or development environment may cause many software developers to resist such approaches due to the difficulty and possible instability of changing well-established robust tool flows. Thus, in the past several years, synthesis from binaries has been introduced, both in research and in commercial tools, as a means of better integrating with tool flows by supporting all high-level languages and software compilers. Binary synthesis can be more easily integrated into a software development tool-flow by only requiring an additional backend tool, and it even enables completely transparent dynamic translation of executing binaries to configurable hardware circuits. In this article, we survey the key technologies underlying the important emerging field of binary synthesis. We compare binary synthesis to several related areas of research, and we then describe the key technologies required for effective binary synthesis: decompilation techniques necessary for binary synthesis to achieve results competitive with source-level synthesis, hardware/software partitioning methods necessary to find critical binary regions suitable for synthesis, synthesis methods for converting regions to custom circuits, and binary update methods that enable replacement of critical binary regions by circuits.
Starting Page 1
Ending Page 30
Page Count 30
File Format PDF
ISSN 10844309
e-ISSN 15577309
DOI 10.1145/1255456.1255471
Volume Number 12
Issue Number 3
Journal ACM Transactions on Design Automation of Electronic Systems (TODAES)
Language English
Publisher Association for Computing Machinery (ACM)
Publisher Date 2008-05-22
Publisher Place New York
Access Restriction One Nation One Subscription (ONOS)
Subject Keyword FPGA Configurable logic Hardware/software codesign Hardware/software partitioning Synthesis from software binaries Warp processors
Content Type Text
Resource Type Article
Subject Computer Graphics and Computer-Aided Design Computer Science Applications Electrical and Electronic Engineering
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