NDLI: The research on optimization techniques of 32-bit floating-point RISC microprocessor

Content Provider	IEEE Xplore Digital Library
Author	Sun Haijun Shao Zhibiao Zou Gang Zhao Ning
Copyright Year	2005
Description	Author affiliation: Sch. of Electron. & Inf. Eng., Xi'an Jiaotong Univ., China (Sun Haijun; Shao Zhibiao; Zou Gang; Zhao Ning)
Abstract	A high-performance low power dissipation 32-bit floating point RISC microprocessor XJ-1 has been successfully fabricated in 0.35 /spl mu/m CMOS technology. A set of innovative optimization techniques are introduced for high performance operation, which include modified redundant Booth-3 algorithm for fast multiplication or division, dynamic SRAM mode control scheme for low power dissipation, embedded bus preselector improving the performance of bus interface, and the large capacity on-chip memory decreasing the amount of traffic with an external memory. These techniques improved the speed and quality with 38% boosted frequency and 39% reduced power dissipation. Each instruction and its random combinations have been tested, and the chip achieves 0.98 mA/MHz at 3.3 V power supply.
Starting Page	63
Ending Page	66
File Size	650897
Page Count	4
File Format	PDF
ISBN	0780390059
DOI	10.1109/IWVDVT.2005.1504465
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Electronic design automation and methodology Microprocessors Random access memory CMOS technology Registers Power dissipation Logic Testing Arithmetic
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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