NDLI: Timing measurement BOST with multi-bit delta-sigma TDC

Content Provider	IEEE Xplore Digital Library
Author	Chujo, T. Hirabayashi, D. Arafune, T. Shibuya, S. Sasaki, S. Kobayashi, H. Tsuji, M. Shiota, R. Watanabe, M. Dobashi, N. Umeda, S. Nakamura, H. Sato, K.
Copyright Year	2015
Description	Author affiliation: Semicond. Technol. Acad. Res. Center, Yokohama, Japan (Tsuji, M.; Shiota, R.; Watanabe, M.; Dobashi, N.; Umeda, S.; Nakamura, H.) \|\| Div. of Electron. & Inf., Gunma Univ., Kiryu, Japan (Chujo, T.; Hirabayashi, D.; Arafune, T.; Shibuya, S.; Sasaki, S.; Kobayashi, H.) \|\| Hikari Sci., Hikari, Japan (Sato, K.)
Abstract	This paper describes design and implementation of a multi-bit delta-sigma (ΔΣ) Time-to-Digital Converter (TDC) with Data-Weighted-Averaging (DWA) algorithm on analog FPGA. I/O interfacing circuits such as double-data-rate (DDR) memory interfaces are very important, and their low-cost, high-quality test is challenging. We propose here simple test circuitry for measuring digital signal timing of I/O interfacing circuits with high resolution and good accuracy. We focus on TDC applications of ΔΣmodulators (for fine-timing-resolution, digital output, and simple circuitry) and with multi-bit architecture (for short testing time). However, the multi-bit ΔΣ TDC suffers from delay mismatches among delay cells. Then we propose to apply the DWA algorithm for the delay cells in order to solve this problem. Our experimental results showed that the DWA algorithm improved the overall multi-bitΔΣ TDC linearity.
Starting Page	1
Ending Page	6
File Size	2339449
Page Count	6
File Format	PDF
ISBN	9781467367325
DOI	10.1109/IMS3TW.2015.7177881
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-24
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device measurement Analog FPGA Time Measurement Linearity Delta-Sigma Time-to-Digital Converter Delays Field programmable gate arrays Signal resolution
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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