NDLI: Program Committee

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2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

2012 International Conference on Reconfigurable Computing and FPGAs

2011 International Conference on Reconfigurable Computing and FPGAs

2010 International Conference on Reconfigurable Computing and FPGAs

2009 International Conference on Reconfigurable Computing and FPGAs

Table of Contents

Message from the Chairs

Program Committee

Additional Reviewers

A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA

FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures

MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs

Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area

A 10 Gbps OTN Framer Implementation Targeting FPGA Devices

FPGA Implementations of BCD Multipliers

Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations

Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture

PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems

A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier

Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation

Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform

A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks

A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance

Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network

FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis

A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA

An FPGA-Based Custom High Performance Interconnection Network

Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000

A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA

Scalability Studies of the BLASTn Scan and Ungapped Extension Functions

Low Power RTL Exploration Mechanism Based on the Cache Parameters

A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation

Low Power, Reconfigurable Computing Platform for Spacecraft

Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure

Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go

Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology

FPGA Implementation of the Generalized Hough Transform

An Optimized System for Multiple Sequence Alignment

Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations

Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules

Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing

Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow

Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation

Lightweight Cryptography for FPGAs

Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units

Observing the Randomness in RO-Based TRNG

DPL on Stratix II FPGA: What to Expect?

FPGA Implementation of an Elliptic Curve Processor Using the GLV Method

Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC

Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath

A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans

Overview of FPGA-Based Multiprocessor Systems

Symmetric Multiprocessor Systems on FPGA

A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip

Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips

Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager

High-Level FPGA Programming through Mapping Process Networks to FPGA Resources

Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers

Composite Look-Up Table Gaussian Pseudo-Random Number Generator

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard

High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor

A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters

Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications

A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements

Enhancing the Productivity of Radio Designers with RapidRadio

Signal Processing Domain Application Mapping on the Brick Reconfigurable Array

Multiprocessor Task Migration Implementation in a Reconfigurable Platform

Virtualization of Computing Resources in RCS for Multi-task Stream Applications

Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time

Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip

New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA

Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA

Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller

A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping

Fuzzy Control for Cyclist Robot Stability Using FPGAs

FPGA Implementation for Direct Kinematics of a Spherical Robot Manipulator

On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion

Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors

Effects of Simplistic Online Synthesis for AMIDAR Processors

A Reconfigurable Design Framework for FPGA Adaptive Computing

Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture

FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition

Publisher's Information

2008 International Conference on Reconfigurable Computing and FPGAs

2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006)

2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig'05)

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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