NDLI: Advanced static verification for SoC designs

Content Provider	IEEE Xplore Digital Library
Author	Ping Yeung Sea Choi
Copyright Year	2009
Description	Author affiliation: Mentor Graphics Corporation, 880 Ridder Park Drive, San Jose, CA, U.S.A. (Ping Yeung) \|\| Mentor Korea Co. Ltd., World Trade Center, Seoul, Kangnam-gu, Korea (Sea Choi)
Abstract	After a design has been implemented in silicon, it is immensely difficult to debug any functional or silicon related problems. Hence, anything that can be done up-front at the RTL or gate-level to prevent errors will be extremely beneficial. So far, simulation-based dynamic verification has been relied upon heavily to verify the functionality of designs. In this paper, we summarize a number of static verification technologies — from simple RTL lint to sophisticated formal property verification — that can complement dynamic verification. These technologies can also help with low power verification and static timing analysis. Most importantly, they can target silicon related problems — such as clock domain crossing uncertainties, X-states, and uninitialized registers — that cannot be verified with dynamic simulation.
Starting Page	295
Ending Page	300
File Size	132706
Page Count	6
File Format	PDF
ISBN	9781424450343
DOI	10.1109/SOCDC.2009.5423785
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-22
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics Uncertainty Feedback Silicon Logic design Performance analysis Timing Clocks Testing Counting circuits
Content Type	Text
Resource Type	Article

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