NDLI: Thermal analysis of 4H-SiC DMOSFET structure under resistive switching

Content Provider	IEEE Xplore Digital Library
Author	Pushpakaran, B.N. Bayne, S.B. Ogunniyi, A.A.
Copyright Year	2014
Description	Author affiliation: Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA (Pushpakaran, B.N.; Bayne, S.B.) \|\| Army Res. Lab., Adelphi, MD, USA (Ogunniyi, A.A.)
Abstract	This research investigates the electro-thermal switching characteristics and lattice temperature profile of a two dimensional (2D) silicon carbide (4H-SiC polytype) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell under resistive switching using Silvaco ATLAS Technology Computer Aided Design (TCAD) physics based simulation software. Physics based models were included to account for recombination effects, bandgap narrowing, low field and high field mobility and lattice heating. The electro-thermal simulation was performed at an ambient lattice temperature of 300K. The device was simulated for 100 $A/cm^{2}$ and 1000 $A/cm^{2}$ drain current densities using a 1 kHz 50% duty cycle gate signal consisting of two cycles and 1.6 kHz 80% duty cycle signal consisting of three cycles. The analysis of lattice temperature profile revealed the formation of thermal hot spots in the vicinity of the (Junction Field Effect Transistor) JFET region in the DMOSFET structure during the switching phase and at the edge of the channel during the conduction phase. The magnitude of temperature rise was dependent on the drain current density used during the simulation.
Starting Page	523
Ending Page	526
File Size	856358
Page Count	4
File Format	PDF
ISBN	9781467373234
e-ISBN	9781479940479
DOI	10.1109/IPMHVC.2014.7287327
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET DMOSFET lattice temperature Lattices Switches silicon carbide silvaco Resistance Heating Logic gates thermal hot spot Current density physics based simulation
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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