NDLI: Dynamic power supply current test for CMOS SRAM

Please wait, while we are loading the content...

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)

ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)

Wireless transceivers in CMOS IC technology. The new wave

Technology frontiers towards the 21st century: embedded DRAM and the system LSIs-process, circuits, and design technology

Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization

A cell selection algorithm for area minimization

Interaction among cost functions in placement

Critical path analysis considering the signal transition time

Optimization of repeater size to minimize interconnect line-induced delay time for high performance VLSI circuits

Design guideline for CMOS drivers with considerations of simultaneous switching noise

Simulation method and application for the hot carrier-induced device degradation of NMOSFET

Systematic calibration for transient enhanced diffusion of indium and its application to 0.15-/spl mu/m logic devices

Profile simulation and stress analysis for optimization of an intermetal dielectric deposition (IMD) process

A new analysis technique for the sensitivity of chip performance

An efficient simultaneous switching noise analysis of high density multi-layer packages and PCBs considering the power and ground planes

Empirical equations on electrical parameters of coupled microstrip lines with one side exposed to air

Interconnect modeling in deep submicron design

Hardware synthesis for stack type partitioned-bus architecture

Hardware cost estimation techniques for C-level description

Wallace-tree based timing-driven synthesis of arithmetic circuits

Co-development of media-processor and source-level debugger using hardware emulation-based validation

Partitioning framework for less restricted partitioning problems

Asynchronous interaction between FSM and dataflow models

Automatic software toolkit generation for embedded systems-on-chip

High density low power full CMOS SRAM cell technology with STI and CVD Ti/TiN barrier metal

Blanket tilt implanted shallow trench isolation (BTI-STI) process for enhanced DRAM retention time characteristics

Metal technology for advanced CMOS devices

New shallow trench isolation scheme with /spl alpha/-Si absorption layer for sub-0.18 /spl mu/m technology

New corner rounding process for sub-0.15 /spl mu/m shallow trench isolation

A high performance 0.13 /spl mu/m CMOS process for GHz microprocessor manufacture

High performance 0.18 um nMOSFET by TED suppression

Evaluation of plasma-induced charging damage on metal contact process

Selective oxide trench etch for dual damascene process in a transformer coupled plasma system

Analysis of sidewall films formed during Si etching with photoresist and nitride mask

High aspect ratio via etching for dual damascene process in a inductively coupled plasma (ICP) etcher

Investigation of half-tone phase shift mask with FIB and blue laser repair

40 nm electron beam patterning and its application to silicon nano-structure fabrication

Simulation of low-energy E-beam lithography

Application of full chip OPC to quarter micron logic device

Experimental investigation of temperature dependent RF performances of RF-CMOS devices

Development of 0.5 /spl mu/m BiCMOS device model library for RFIC applications

DRAM technology: outlook and challenges

Silicon MOS memory with self-aligned quantum dot on narrow channel

A bias dependent source/drain resistance model in LDD MOSFET devices for distortion analysis

A study on soft- and hard-breakdowns in MOS capacitors using the parallel stressing method

Improved small-signal modeling of RF Si MOSFETs

Interconnect technology: copper and low-k dielectrics

Advanced interconnect technologies for ULSI scaling

CoSi/sub 2/ junction leakage with Ti or TiN capping, and device characteristics in embedded DRAM with stack capacitor

Optical sensitivity and barrier property depending on ILD layers of CMOS image sensor device

Investigations in polysilicon CMP to apply in sub-quarter micron DRAM device

HOSP(R) as a low dielectric material: comparative study against hydrogen silsesquioxane

Optimum barrier layer for Al-PMD (preferential metal deposition) process

Denuded-WN/sub x//poly-Si gate technology for deep sub-micron CMOS

XPS analysis of RTP formed ultrathin-gate oxynitride via low energy nitrogen implantation

Comparison of the characteristics of tunneling oxide and tunneling ON for p-channel nano-crystal memory

Application of low-temperature N/sub 2/O-annealed oxide and chemical oxide for both boron penetration and gate depletion reductions for thin p/sup +/ tungsten polycide gate

The effects of post annealing on oxide-charge-to-breakdown and interface state in tungsten polycide gate

Ultra thin-oxide damage from gate charging during PETEOS deposition processing

Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process

Device characteristics and reliability for 0.18 /spl mu/m MOSFET with 20 /spl Aring/ gate oxide formed by RTO

A pipelined row address decoding scheme for hierarchical word line structure DRAM

A digital temperature compensated crystal oscillator using a temperature adaptive capacitor array

Current status of PPRAM

7.1 GB/sec bandwidth 3D rendering engine using the EML technology

A novel cell charge evaluation scheme and test method for 4 Mb nonvolatile ferroelectric RAM

A fast synchronous pipelined DRAM (SP-DRAM) architecture with SRAM buffers

A bootstrapped CMOS circuit technique for low-voltage application

High speed code acquisition for wideband CDMA system

Lower power Viterbi decoder architecture with a new clock-gating trace-back unit

An efficient turbo decoder architecture for IMT2000

Design of a combined processor containing a 32-bit RISC microprocessor and a 16-bit fixed-point DSP on a chip

A 2048 complex point FFT processor for DAB systems

A hardware efficient VLSI implementation of MPEG-4 format conversion filters

Low-power TFT-LCD source driver using triple charge sharing method

High performance CMOS dual-modulus prescaler using selective latch technique

LSI design toward 2010 and low-power technology

A novel double slope analog-to-digital converter for a high-quality 640/spl times/480 CMOS imaging system

A 4-400 MHz jitter-suppressed delay-locked loop with frequency division method

Digitally-controlled automatic gain control circuits for CMOS CCD electronic cameras

A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter

Switched-capacitor circuit techniques in submicron low-voltage CMOS

Low power CMOS digital design for multimedia processors

An integrated CDMA intermediate-frequency transceiver for 10-MHz wireless local loop

Design and implementation of L1-band C/A-code GPS RF front-end chip

Enhanced ACPR technique by class AB in PCS driver amplifier

A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X

A sense amplifier-based CMOS flip-flop with an enhanced output transition time for high-performance microprocessors

High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme

Retiming for high speed and low power design

Dynamic power supply current test for CMOS SRAM

A SPICE compatible single electron transistor (SET) transient model

Skew optimization by combining tree-based and graph-based techniques for high performance clock routing

Development of technology mapping algorithm for CPLD under time constraint

Equivalent circuit extraction from the measured S-parameters of electronic packages

A precipitation modeling of implantation induced defects

TCAD simulation of the nitrogen effect by NO-nitrided oxide

Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology

A single transistor ferroelectric RAM with nondestructive readout operations

Warpage effect on breakdown voltage of DRAM device

Improved etching technique of E-ICP (Enhanced Inductively Coupled Plasma)

Characteristics of interconnect lines with patterned ground shields and its implication for microwave ICs

Effects of N/sub 2/ addition on aluminum alloy etching: optical emission spectroscopy studies

Enhancing uniformity of borderless via resistance by HDP oxide technology

Dishing and erosion in STI CMP

Identification and removal of defects on silicon wafer processed with a rinse with/without megasonics in DI water

Generation of trench dislocation in 0.25 /spl mu/m logic technology and its elimination

W CMP evaluation for 0.25 /spl mu/m logic device

A simple method for formation of the buffer layer in n-channel LDMOS

The effect of ILD material and BPSG densification anneal on the device characteristics

Dramatic reduction of plasma induced damage using 2-step power down method in metal etch process

Thermally stable W-bit line technology for ULSI device application

The halo nMOSFET characteristics dependent on the gate profile

Improvement of hot carrier lifetime by cleaning process prior to selective reoxidation in metal gate LDD nMOSFETs

The effects of development parameter on line edge roughness in sub-0.20 /spl mu/m line patterns

Effect of CMP process on alignment accuracy

Plasma induced charging damage on thin gate oxide

Growth of RuO/sub x/ thin films by metalorganic chemical vapor deposition

Improved planarization method using sandwiched hard layer (SHaL) CMP

Novel Al/sub 2/O/sub 3/ capacitor for high density DRAMs

Experimental stress analysis for flip chip BGA packages using strain gauge

Current problems of high energy application in memory device fabrication

Scalable threshold voltage model for deep-submicrometer MOSFET

Code generation for embedded processors with complex instructions

Fault sensitivity analysis of a 32-bit RISC microprocessor

Design of an 8-bit neuron MOSFET A/D converter using subranging method

High speed, energy efficient master-slave flip-flops

Self-timed shared division and square-root implementation using full redundant signed digit numbers

A multi-threading MPEG processor with variable issue modes

Interleaving partial bus-invert coding for low power reconfiguration of FPGAs

A folded bit-line architecture for high speed CMOS SRAM

A design of 2-D DCT/IDCT for real-time video applications

Self-timed statistical carry lookahead adder using multiple-output DCVSL

A fast lock-on time mixed mode DLL with 10 ps jitter

WLL base station modem ASIC

Design of the voltage clamp delay cell VCO using quadrature phase for low phase noise and high speed operation

A high-speed 50% power-saving half-swing clocking scheme for flip-flop with complementary gate and source drive

A low-complexity VLSI architecture of multidimensional TCM decoder for ADSL

A design of fast searcher for CDMA WLL system

Two-phase boosted voltage generator [CMOS DRAMs]

POPeye: a system analysis tool for DRAM performance measurement

A digital convergence system using cubic splines

A novel charge pump PLL with reduced jitter characteristics

The CMOS temperature sensor and cyclic ADC for low power single chip DTCXO

A BISR (built-in self-repair) circuit for embedded memory with multiple redundancies

Swallow counterless DMP PLL

Double precharge TSPC for high-speed dual-modulus prescaler

Dynamic power supply current test for CMOS SRAM

Content Provider	IEEE Xplore Digital Library
Author	Doe Hyun Yoon Hong Sik Kim Sungho Kang
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea (Doe Hyun Yoon)
Abstract	This paper presents the relationship between the dynamic power supply current and the switching behavior of an SRAM cell. Compared to a fault free cell, how the short, open and coupling faults can affect the peak value of a dynamic current pulse when a transition write is performed, is analyzed. In addition, the test for linked idempotent coupling faults is proposed. This new approach has reduced test length compared to the previous March B test. Finally the low overhead built-in current sensor that can detect a dynamic current pulse and distinguish its peak value, is proposed.
Starting Page	399
Ending Page	402
File Size	355665
Page Count	4
File Format	PDF
ISBN	0780357272
DOI	10.1109/ICVC.1999.820944
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-26
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power measurement Power supplies Pulsed power supplies Current measurement Random access memory Electronic equipment testing Current supplies Circuit faults Circuit testing Logic testing
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in