NDLI: Enhancement of the weight cell utilization for CMAC neural networks: architecture design and hardware implementation

Content Provider	IEEE Xplore Digital Library
Author	Jar-Shone Ker Rong-Chang Wen Yau-Hwang Kuo Bin-Da Liu
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Jar-Shone Ker)
Abstract	CMAC neural network model has the advantages of fast learning and insensitivity to the order of presentation of training data. However, it may suffer from a huge storage requirement for realizing the weight cell memory. In this paper, we propose a memory banking structure and a direct weight cell address mapping scheme, which can sharply reduce the required address space of weight cell memory. This mapping scheme also exhibits a fast computation speed in generating weight cell addresses. Besides, a pipelined architecture is developed to realize the CMAC chip. To efficiently manage design complexity and increase design productivity and maintainability, a high-level synthesis technique is adopted to perform the task of logic design of the CMAC chip.
Starting Page	244
Ending Page	251
File Size	723042
Page Count	8
File Format	PDF
ISBN	0818667109
DOI	10.1109/ICMNN.1994.593716
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-09-26
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Productivity Neural networks Training data Signal processing algorithms Banking Brain modeling Hardware High level synthesis Function approximation Guidelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A CMAC neural network chip for color correction

A fuzzy CMAC structure and learning method for function approximation

A hierarchical CMAC architecture for context dependent function approximation

CMAC neural networks structures

Generalizing CMAC architecture and training

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

Vibration control using CMAC neural networks with optimized weight smoothing

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems

Two dimensional function learning using CMAC neural network with optimized weight smoothing

Enhancement of the weight cell utilization for CMAC neural networks: architecture design and hardware implementation

Similar Documents

A CMAC neural network chip for color correction

A fuzzy CMAC structure and learning method for function approximation

A hierarchical CMAC architecture for context dependent function approximation

CMAC neural networks structures

Generalizing CMAC architecture and training

Bit-Width Aware High-Level Synthesis for Digital Signal Processing Systems

Vibration control using CMAC neural networks with optimized weight smoothing

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems

Two dimensional function learning using CMAC neural network with optimized weight smoothing

Enhancement of the weight cell utilization for CMAC neural networks: architecture design and hardware implementation