NDLI: A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration

Content Provider	IEEE Xplore Digital Library
Author	Zhan Xu Xiao Wu Yi Wu
Copyright Year	2013
Description	Author affiliation: Sch. of Comput. Sci. & Eng., NorthWestern Polytech. Univ., Xi'an, China (Zhan Xu; Xiao Wu; Yi Wu)
Abstract	Now in the field of embedded system, high-speed interconnection based on parallel or serial LVDS technology is becoming increasingly important. Because of this the first RapidIO offerings available in the market were FPGA based, RapidIO interconnection had been identified as significant emerging technologies for FPGAs to support. At the same time, as the FPGAs increase in size, they are being large enough to accommodate both the static RapidIO interface and the reconfigurable logic. So, a consistent I/O interface is provided to support Reconfigurable Partition. This paper presents a new system interconnection architecture based on RapidIO to achieve the FPGA run-time Reconfigurable Partition.
Starting Page	275
Ending Page	279
File Size	293017
Page Count	5
File Format	PDF
e-ISBN	9781479933815
DOI	10.1109/DASC.2013.75
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors RapidIO Interconnection FPGA Switches Routing Registers Reconfigurable Partition Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration