NDLI: 1024-point pipeline FFT processor with pointer FIFOs based on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Guanwen Zhong Hongbin Zheng ZhenHua Jin Dihu Chen Zhiyong Pang
Copyright Year	2011
Description	Author affiliation: School of physics and engineering, Sun Yat-sen University, Guangzhou 510275, China (Guanwen Zhong; Hongbin Zheng; ZhenHua Jin; Dihu Chen; Zhiyong Pang)
Abstract	Design and optimized implementation of a 16-bit and 32-bit 1024-point pipeline FFT processor is presented in this paper. The architecture of the FFT is based on $R2^{2}SDF$ algorithm with new pointer FIFO embedded with gray code counters. It is implemented in Spartan-3E, Spartan-6 and Virtex-4 devices and fully tested by method of co-simulation using $SMIMS^{®}$ $VeriLink^{®}$ as a bridge that connects $software(Matlab^{®}$ $Simulink^{®})$ and real hardware-FPGA targets. The implementation results show that our pointer FIFO FFT processor could use lower resource, but achieve higher performance. Our 16-bit 1024-point FFT processor only costs 2580 slices, 2030 slice flip flops and just 2 block RAMs, achieving the maximum clock frequency of 92.6 MHz with the throughput per area of 0.035 Msamples/s/area. Due to the parameterized input wordlength, output wordlength, Twiddle Factors wordlength and processing stages, it is easily to implement a 16-point, 64-point, 256-point, 1024-point,4096-point or higher power of 4 points pointer FIFO FFT processor synthesized from the same code just through modifying the corresponding parameters.
Starting Page	122
Ending Page	125
File Size	1387398
Page Count	4
File Format	PDF
ISBN	9781457701719
e-ISBN	9781457701702
e-ISBN	9781457701696
DOI	10.1109/VLSISoC.2011.6081654
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-03
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pointer FIFO Radiation detectors Pipelines FFT Random access memory $Radix2^{2}SDF$ Computer architecture Throughput Reflective binary codes Cosimulation Field programmable gate arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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