NDLI: On-chip timing slack monitoring

Content Provider	IEEE Xplore Digital Library
Author	Rebaud, B. Belleville, M. Beigne, E. Robert, M. Maurine, P. Azemard, N.
Copyright Year	2009
Description	Author affiliation: LIRMM - CNRS - Université Montpellier II, 161 rue Ada, 34392, FRANCE (Robert, M.; Maurine, P.; Azemard, N.) \|\| CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE (Rebaud, B.; Belleville, M.; Beigne, E.)
Abstract	PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper describes a new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special structures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily insertable in a standard CAD flow.
Starting Page	89
Ending Page	94
File Size	878873
Page Count	6
File Format	PDF
ISBN	9781457702372
e-ISBN	9781457702365
DOI	10.1109/VLSISOC.2009.6041336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-12
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Latches timing slack Image edge detection process compensation Variability monitor Timing Sensors Monitoring Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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