NDLI: A polymorphic 15GHz/mW inductorless frequency prescaler using implication logic in 0.13μm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Roa, E. Wu-Hsin Chen Byunghoo Jung
Copyright Year	2012
Description	Author affiliation: Qualcomm San Diego, CA (Wu-Hsin Chen) \|\| School of Electrical and Computer Engineering - Purdue University (Roa, E.; Byunghoo Jung)
Abstract	This paper describes a power-efficient frequency prescaler operating at maximum frequency of 12.3GHz without using inductors. A novel logic concept and reconfigurable technique is presented to achieve two division factors by using just one single-phase clock flip-flop. The prescaler is implemented in 0.13μm CMOS technology. It occupies $14×12μm^{2}$ and consumes 817μW at maximum frequency. Experimental results indicate a power efficient and compact frequency divider working in wide frequency range from 5GHz to 12.3GHz.
Starting Page	71
Ending Page	73
File Size	514653
Page Count	3
File Format	PDF
ISBN	9781467323031
e-ISBN	9781467323055
DOI	10.1109/RFIT.2012.6401617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-21
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise PLL design Latches Single-Phase clock Logic gates Frequency conversion Frequency divider CMOS integrated circuits Frequency measurement Clocks dual-modulus prescaler
Content Type	Text
Resource Type	Article

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A polymorphic 15GHz/mW inductorless frequency prescaler using implication logic in 0.13μm CMOS