NDLI: Disruptive design solutions for frequency generation in silicon RFIC

Content Provider	IEEE Xplore Digital Library
Author	Deval, Y. Mazouffre, O. Majek, C. Lapuyade, H. Taris, T. Begueret, J.-B.
Copyright Year	2005
Description	Author affiliation: IXL Lab., Bordeaux I Univ., Talence, France (Deval, Y.; Mazouffre, O.; Majek, C.; Lapuyade, H.; Taris, T.; Begueret, J.-B.)
Abstract	This paper presents some new approaches for frequency generation in silicon RF integrated circuits, from either the circuit or the architecture point of view. While a phase locked loop (PLL) is classically brought into play whenever a frequency synthesis is needed, the design of key building blocks such as the RF frequency divider is a very challenge. Concerning the latter, the synchronized ring oscillator (SRO), which provides dual-modulus division at frequency above 20 GHz while consuming little power, is presented. Alternative solutions to the classical PLL, such as injection locked oscillator (ILO) and factorial delay locked loop (F-DLL) are presented as well. Advantages and drawbacks of these approaches are discussed, based upon simulation and experimental measurements.
Starting Page	97
Ending Page	100
File Size	2171765
Page Count	4
File Format	PDF
ISBN	0780393724
DOI	10.1109/RFIT.2005.1598883
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-30
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit synthesis Ring oscillators Frequency synthesizers DLL RFIC Frequency Generation Frequency conversion Phase locked loops Radio frequency PLL Injection-locked oscillators Silicon Radiofrequency integrated circuits Frequency synchronization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers

A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications

Design of serial input PLL frequency synthesizer

A Monolithic Digital Frequency Synthesizer for PLL Systems

A high-speed variable phase accumulator for an ADPLL architecture

An integrated low-noise CMOS PLL frequency synthesis

A study of high-frequency regenerative frequency dividers

CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Disruptive design solutions for frequency generation in silicon RFIC

Similar Documents

CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers

A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications

Design of serial input PLL frequency synthesizer

A Monolithic Digital Frequency Synthesizer for PLL Systems

A high-speed variable phase accumulator for an ADPLL architecture

An integrated low-noise CMOS PLL frequency synthesis

A study of high-frequency regenerative frequency dividers

CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications

Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits

Disruptive design solutions for frequency generation in silicon RFIC