NDLI: Optimizing dynamic-threshold DTMOS device performance in an SOI embedded DRAM technology

Content Provider	IEEE Xplore Digital Library
Author	Burke, F. Kim, C.S. Rambhatla, A. Zhao, Y. Zahurak, J. Parke, S.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Boise State Univ., ID, USA (Burke, F.; Kim, C.S.; Rambhatla, A.; Zhao, Y.)
Abstract	This paper describes the DC and high frequency characteristics of a dynamic threshold DTMOS n-channel device, fabricated within a low-cost CMOS SOC process which also includes high-density embedded DRAM. The DTMOS device design in this process was previously found to be superior to both grounded body (GB) and floating body (FB) MOSFETs. This DTMOS device achieves kink-free behavior, with gm=936 /spl mu/S//spl mu/m, g/sub out/=36 /spl mu/S//spl mu/m, Ion/Ioff=210 /spl mu/A/0.1 pA, S=67 mV/dec, and fmax=32 GHz at V/sub DD/=1 V. These DTMOS devices are excellent for sub-volt embedded baseband circuits with sufficient performance for RF front-end circuits, thus enabling the combination of embedded DRAM, digital, analog, and RF circuit cores in, ultra-low-power, low-cost SOCs.
Sponsorship	IEEE Electron Devices Soc. Micron Found. IEEE EDS Boise Chapter Boise State Univ
Starting Page	292
Ending Page	294
File Size	143654
Page Count	3
File Format	PDF
ISBN	0780379721
ISSN	07496877
DOI	10.1109/UGIM.2003.1225746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Radio frequency MOSFETs MOS devices CMOS technology CMOS process Parasitic capacitance Transconductance Circuit testing System testing
Content Type	Text
Resource Type	Article

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