NDLI: An efficient lid design for cooling stacked flip-chip 3D packages

Content Provider	IEEE Xplore Digital Library
Author	Sikka, K. Wakil, J. Toy, H. Hsichang Liu
Copyright Year	2012
Description	Author affiliation: Packaging and Semiconductor Research and Development Center, IBM Systems and Technology Group, 2070 Route 52, Hopewell Jn, NY 12533, USA (Sikka, K.; Wakil, J.; Toy, H.; Hsichang Liu)
Abstract	3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.
Starting Page	606
Ending Page	611
File Size	427291
Page Count	6
File Format	PDF
ISBN	9781424495337
ISSN	10879870
e-ISBN	9781424495320
e-ISBN	9781424495313
DOI	10.1109/ITHERM.2012.6231484
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermal resistance Conductivity Thermal sensors Electronic packaging thermal management Thermal conductivity Standards efficient lid design 3D package thermal management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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