NDLI: Achieving High Test Quality with Reduced Pin Count Testing

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TTTC Introduction

TTEP Introduction

T1: Design for Manufacturability

T2: Statistical Methods for VLSI Test and Burn-in Optimization

Design for Testability: The Path to Deep Submicron

DFT Aware Layout - Layout Aware DFT

Embedded Test Technology - Brief History, Current Status, and Future Directions

Faults and Tests in Quantum Circuits

Improving Logic Test Quality of Microprocessors

Robust Built-In Test of RF ICs Using Envelope Detectors

Delay Defect Characterization Using Low Voltage Test

Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester

IDDQ Testing Method using a Scan Pattern for Production Testing

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications

Block-based Schema-driven Assertion Generation for Functional Verification

A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor Cores

The Automatic Generation of Basis Set of Path for Path Testing

Optimal Schemes for ADC BIST Based on Histogram

A 5 Gbps Wafer-Level Tester

Low-cost Production Test of BER for Wireless Receivers

Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors

A State Machine for Detecting C/C++ Memory Faults

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models

Boundary Value Testing based on UML Models

Random Jitter Testing Using Low Tap-Count Delay Lines

Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle

A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects

Non-robust Test Generation for Crosstalk-Induced Delay Faults

Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST

Circuit Independent Weighted Pseudo-Random BIST Pattern Generator

Low Transition LFSR for BIST-Based Applications

A BIST Scheme Based on Selecting State Generation of Folding Counters

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression

SOC Test Scheduling with Test Set Sharing and Broadcasting

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

Flash Memory Die Sort by a Sample Classification Method

Chip Identification using the Characteristic Dispersion of Transistor

Untestable Multi-Cycle Path Delay Faults in Industrial Designs

Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions

Selection of Paths for Delay Testing

On Improving Defect Coverage of Stuck-at Fault Tests

A Scan Matrix Design for Low Power Scan-Based Test

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing

Partial Gating Optimization for Power Reduction During Test Application

Bridge Defect Diagnosis with Physical Information

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths

A Class of Linear Space Compactors for Enhanced Diagnostic

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size

Enhancing Fault Simulation Performance by Dynamic Fault Clustering

Cost Optimal Design of Nonlinear CA based PRPG for Test Applications

An Effective Design for Hierarchical Test Generation Based on Strong Testability

Concurrent Test Generation

Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency

Achieving High Test Quality with Reduced Pin Count Testing

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing

Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency

Efficient Test Compaction for Pseudo-Random Testing

Test Data Compression with Partial LFSR-Reseeding

CryptoScan: A Secured Scan Chain Architecture

Pseudo-Parity Testing with Testable Design

Finite State Machine Synthesis for At-Speed Oscillation Testability

A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor

Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation

Low Power Test Compression Technique for Designs with Multiple Scan Chain

Threshold testing: Covering bridging and other realistic faults

Synthesis of Testable Finite State Machine Through Decomposition

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability

Flip-flop chaining architecture for power-efficient scan during test application

A Unified Approach to Partial Scan Design using Genetic Algorithm

A Family of Logical Fault Models for Reversible Circuits

Compressing Functional Tests for Microprocessors

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach

Arithmetic Test Strategy for FFT Processor

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation

IEEE Std 1500 Compliant Infrastructure forModular SOC Testing

DFT for Low Cost SOC Test

Managing Test and Repair of Embedded Memory Subsystem in SoC

The Ultimate Chase

Defect-Oriented Test for Ultra-Low DPM

Current Testing for Nanotechnologies: A Demystifying Application Perspective.

High Level Test Generation for Custom Hardware: An Industrial Perspective

High Level Test Generation / SW based Embedded Test

Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes

Emerging Techniques for Test Data Compression

Improving Test Quality Using Test Data Compression

Efficient Test Architecture based on Boundary Scan for Comprehensive System Test

Challenges in Next Generation Mixed-Signal IC Production Testing

Practices in Testing of Mixed-Signal and RF SoCs

Challenges in High Speed Interface Testing

Practical Aspects of Delay Testing for Nanometer Chips

Limitation of structural scan delay test

Shortening Burn-In Test: Application of a Novel Approach in optimizing Burn-In Time using Weibull Statistical Analysis with HVST

ATS 2006 Call for Papers

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

Achieving High Test Quality with Reduced Pin Count Testing

Content Provider	IEEE Xplore Digital Library
Author	Jahangiri, J. Mukherjee, N. Wu-Tung Cheng Mahadevan, S. Press, R.
Copyright Year	2005
Description	Author affiliation: Mentor Graphics Corporation,Wilsonville, OR (Jahangiri, J.)
Abstract	Reduced pin count testing (RPCT) has proven to be an effective solution to reduce structural test costs in a manufacturing environment. Traditionally, RPCT has focused on stuck-at faults and IO loop-back tests. However, as circuit feature sizes shrink and new technology nodes employed, at-speed tests are becoming critical to assure low defect levels. In this paper, we extend the RPCT technique to allow application of atspeed test patterns using low cost testers that are seriously pin limited. Existing boundary scan cells are modified to facilitate the application of at-speed patterns thereby having minimal impact on the design and test area overhead.
Starting Page	312
Ending Page	317
File Size	508688
Page Count	6
File Format	PDF
ISBN	0769524818
ISSN	10817735
DOI	10.1109/ATS.2005.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-18
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Costs Circuit faults Manufacturing Pins Packaging Frequency Performance evaluation Probes Time to market
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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