NDLI: A simple wrapped core linking module for SoC test access

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A simple wrapped core linking module for SoC test access

Content Provider	IEEE Xplore Digital Library
Author	Jaehoon Song Sungju Park
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Hanyang Univ., South Korea (Jaehoon Song; Sungju Park)
Abstract	For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC) Tech. Group on Dependable Comput. IEICE Special Interest Group on Syst. LSI Design Methodology IPS Japan
Starting Page	344
Ending Page	349
File Size	466598
Page Count	6
File Format	PDF
ISBN	0769518257
ISSN	10817735
DOI	10.1109/ATS.2002.1181735
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Joining processes Pins System testing Logic testing Logic design Switches Computer science Signal design Registers Digital signal processing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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