NDLI: Concurrent control of multiple BIT structures

Content Provider	IEEE Xplore Digital Library
Author	Breuer, M.A. Gupta, R. Lien, J.-C.
Copyright Year	1988
Description	Author affiliation: Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA (Breuer, M.A.; Gupta, R.; Lien, J.-C.)
Abstract	A generic control graph for activating common built-in test structures is derived and its microprogrammed and hardwired implementations described. Three designs for activating multiple BIT structures concurrently are also presented along with simulation results of area/test time tradeoffs. Two designs for this generic controller are presented. The first design augments the classical microprogrammed controller with some circuitry used for counting. This design is most useful when a microprogrammable controller already exists for normal control operations. The second design is a hardwire unit which efficiently implements the generic controller. A complete circuit-level implementation is described. The controller can be easily made self-testing by modifying an existing register to support signature analysis. In addition, the controller is quite simple and can be incorporated on-chip.
Starting Page	431
Ending Page	442
File Size	880672
Page Count	12
File Format	PDF
ISBN	0818608706
ISSN	10893539
DOI	10.1109/TEST.1988.207754
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Logic testing Very large scale integration Built-in self-test Very high speed integrated circuits Design for testability System testing Signal processing Design methodology Logic design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Applied Mathematics

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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