NDLI: Logic mapping on a microprocessor

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Logic mapping on a microprocessor

Content Provider	IEEE Xplore Digital Library
Author	Kinra, A. Balachandran, H. Thomas, R. Carulli, J.
Copyright Year	2000
Description	Author affiliation: Texas Instrum. Inc., Stafford, TX, USA (Kinra, A.)
Abstract	Improving debug techniques for logic failures is a constant imperative. This paper describes the results of implementing a logic mapping methodology that integrates in-line manufacturing defect data and scan-based diagnosis for a complex microprocessor. The correlation between the physical failure analysis results and defect inspection data is presented and analyzed. Methods to improve the percentage of 'hits' are explored, supported by a detailed account of challenges and obstacles encountered during the experiment. Finally, the paper also briefly highlights the amount of time that can be saved in process debug through the usage of logic mapping.
Starting Page	701
Ending Page	710
File Size	1105897
Page Count	10
File Format	PDF
ISBN	0780365461
ISSN	10893539
DOI	10.1109/TEST.2000.894265
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Failure analysis Inspection Logic devices Logic arrays Throughput Time measurement Instruments Pulp manufacturing Textile industry
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Applied Mathematics

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