NDLI: System-on-chip design beyond 50 GHz

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2006 6th International Workshop on System on Chip for Real Time Applications

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

Proceedings. Fifth International Workshop on System-on-Chip for Real-Time Applications

Open HW, open design SW, and the VC ecosystem dilemma

Enabling technology for analog integration

System-on-chip design beyond 50 GHz

Strained Si and the future direction of CMOS

HW/SW co-design for SoC on mobile platforms

A methodology for HW/SW specification and simulation at multiple levels of abstraction

A software/hardware platform for rapid prototyping of video and multimedia designs

The software-hardware co-debug environment with emulator

DfM for SoC (design-for-manufacturability for system on a chip)

ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs

System on chip: challenges and design for manufacturing

Leakage current variability in nanometer technologies

Generic modeling of nonplanar dielectrics for 2 1/2D parasitic extraction

Flash memories for SoC: an overview on system constraints and technology issues

Four-valued memory circuit designed by multiple-peak MOS-NDR devices and circuits

PLL-based fractional-N frequency synthesizers

A new topology for power control of high efficiency class-E switched mode power amplifier

A CMOS quality factor enhanced parallel resonant LC-tank with independent Q and frequency tuning for RF integrated filters

A novel clock recovery scheme with improved jitter tolerance for PAM4 signaling

A very low-power flash A/D converter based on CMOS inverter circuit

Bidirectional current-mode capacitor multiplier in DC-DC converter compensation

Design of 12-bit 100-MHz current-steering DAC for SOC applications

A power efficient decoder for 2GHz, 6-bit CMOS flash-ADC architecture

A comprehensive model for on-chip spiral inductors

Design and optimization of low-voltage low-power quasi-floating gate digital circuits

Life-inspired systems: assuring quality in the era of complexity

Evolution of bootstrap techniques in low-voltage CMOS digital VLSI circuits for SOC applications

A review of common receive-end adaptive equalization schemes and algorithms for a high-speed serial backplane

Sigma-delta noise shaping for digital-to-frequency and digital-to-RF-amplitude conversion

Improved wideband low distortion cascaded delta-sigma modulator

Noise analysis of a CMOS active pixel sensor for tomographic mammography

Conversion time analysis of time domain digital pixel sensor in uniform and non-uniform quantizers

A temperature, supply voltage compensated floating-gate MOS dosimeter using V/sub TH/ extractor

A pH-ISFET based micro sensor system on chip using standard CMOS technology

A very low power CMOS potentiostat for bioimplantable applications

An acoustic echo canceller chip

A high-performance error concealment processor for video decoder

A scalable low power imager architecture for compound-eye vision sensors

UMHexagonS algorithm based motion estimation architecture for H.264/AVC

A hardware-accelerated framework with IP-blocks for application in MPEG-4

Digital RF processing techniques for SoC radios (invited)

Low power Bluetooth for headset applications

Design of 802.11 access point chipsets for enterprise applications

VHDL simulation and modeling of an all-digital RF transmitter

Efficient pattern-based emulation for IEEE 802.11a baseband

A 2.3GHz CMOS transimpedance preamplifier for optical communication

A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz

Design, mapping, and simulations of a 3G WCDMA/FDD base station using network on chip

Tier 3 software defined AM radio

A stochastic power-supply noise reduction technique using max-flow algorithm and decoupling capacitance

A structure based clustering algorithm with applications to VLSI physical design

Global lower bounds for the VLSI macrocell floorplanning problem using semidefinite optimization

Enhancing performance and saving energy in CMOS DCVSL gates by using a new transistor sizing algorithm

Component-based methodology for hardware design of a dataflow processing network

An automatic layout generator for I/O cells

Additional knowledge of bus invert coding schemes

High level extraction of SoC architectural information from generic C algorithmic descriptions

Practical techniques for performance estimation of processors

A multilevel eigenvalue based circuit partitioning technique

A hybrid distributed test generation method using deterministic and genetic algorithms

Accelerating functional simulation for processor based designs

Instruction based testbench architecture

A precise model for leakage power estimation in VLSI circuits

Turbo codes - digital IC design

A low area and low power programmable baseband processor architecture

Power saving of a dynamic width controller for a monolithic current-mode CMOS DC-DC converter

An optimal ILP model for delay time to minimize peak power and area

Power reduction technique using multi-Vt libraries

A low-power partitioning methodology by maximizing sleep time and minimizing cut nets

Novel voltage-controlled oscillator design by MOS-NDR devices and circuits

An area-efficient high-speed AES S-box method

Low latency and power efficient VD using register exchanged state-mapping algorithm

A novel design of a 6-GHz 8 /spl times/ 8-b pipelined multiplier

Logic circuit design based on MOS-NDR devices and circuits fabricated by CMOS process

An area-reduced scheme for modulo 2/sup n/-1 addition/subtraction

Very high radix scalable Montgomery multipliers

A fast full search equivalent encoding algorithm for image vector quantization based on the WHT and a LUT

Low-power programmable signal processing

An FPGA based accelerator for SAT based combinational equivalence checking

A field-programmable analog array using translinear elements

Hardware acceleration of deadlock avoidance and detection in real-time operating systems

System-level analog simulation of a mixed-signal continuous-time field programmable analog array

FPGA implementation of digital controller for DC-DC buck converter

Systolic array-based string matching unit for spam blocking

An FPGA design of a unified hash engine for IPSec authentication

Performance improvement of configurable processor architectures using a variable clock period

Programmable low dropout voltage regulator

Three dimensional system on chip technology

Simulation and analysis of network on chip architecture for wireless communication system

Recent advances and future trends in low power wireless systems for medical applications

Floating-gate devices, circuits, and systems

10 GBPS over copper lines - state of the art in VLSI

A review of current standards activities for high speed physical layers

Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications

A high efficiency 3GHz 24-dBm CMOS linear power amplifier for RF application

A 20 Gbps scalable load-balanced TDM switch with CODEC for high speed networking applications

High-speed serial links: design trends and challenges

Synchronous pipelined relay stations with back-pressure tolerance

Modular architecture for system-on-chip design of scalable MEMS optical switch actuator controller

Architecture for multi-processor SoC platform using dedicated channels

Implementation of an on-chip bus bridge between heterogeneous buses with different clock frequencies

Traffic configuration for evaluating networks on chips

Orthogonalized communication architecture for MP-SoC with global bus

MP SoCs including optical interconnect: technological progresses and challenges for CAD tools design

Transaction analysis of multiprocessor based platform with bus matrix

A generic method for embedded measurement and compensation of process and temperature variations in SOCs

4th IEEE International Workshop on System-on-Chip for Real-Time Applications

The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.

System-on-chip design beyond 50 GHz

Content Provider	IEEE Xplore Digital Library
Author	Voinigescu, S.P. Gordon, M. Lee, C. Yao, T. Mangan, A. Yau, K.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada (Voinigescu, S.P.; Gordon, M.; Lee, C.; Yao, T.; Mangan, A.; Yau, K.)
Abstract	Candidate topologies and design methodologies for millimeter-wave IC building blocks such as LNAs, mixers, VCOs, and power amplifiers are discussed and recent experimental results obtained in SiGe BiCMOS and 90-nm RF CMOS technologies using inductors and transformers above 50 GHz are presented.
Sponsorship	iCore Western Econ. Diversification Canada Alberta Innovation & Sci. Ind. Canada CMC Microsystems
Starting Page	10
Ending Page	13
File Size	371976
Page Count	4
File Format	PDF
ISBN	0769524036
DOI	10.1109/IWSOC.2005.103
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-20
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip BiCMOS integrated circuits CMOS technology Topology Design methodology Millimeter wave technology CMOS integrated circuits Radiofrequency integrated circuits Power amplifiers Radiofrequency amplifiers
Content Type	Text
Resource Type	Article

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