NDLI: A fully-integrated 860-GHz CMOS terahertz sensor

Content Provider	IEEE Xplore Digital Library
Author	Zhao-yang Liu Li-yuan Liu Jie Yang Nan-jian Wu
Copyright Year	2015
Description	Author affiliation: State Key Lab. of Superlattices & Microstructures, Inst. of Semicond., Beijing, China (Zhao-yang Liu; Li-yuan Liu; Jie Yang; Nan-jian Wu)
Abstract	This paper proposes a fully-integrated 860-GHz terahertz wave sensor. The sensor integrates a terahertz detector and readout circuit in 180-nm standard CMOS process. The readout circuit consists of a low-noise instrumentation amplifier and a high-resolution ΔΣ-ADC. Transmissive imaging without source modulation (no lock-in technique required) is realized using the sensor. The detector consists of a novel on-chip grounded patch antenna, a source-feeding NMOS field effect transistor and matching networks. A quarter-wavelength microstrip transmission line is designed to connect the gate of the NMOS transistor to eliminate the influence of bonding wire and pad. The measured maximum voltage responsivity $(R_{v})$ and minimum noise equivalent power (NEP) of the detector at 860 GHz are 3.3 kV/W and 106 $pW/Hz^{1/2},$ respectively. The measured readout circuit noise is 2. 03 μVrms.
Starting Page	1
Ending Page	4
File Size	737775
Page Count	4
File Format	PDF
ISBN	9781467371919
DOI	10.1109/ASSCC.2015.7387437
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-09
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors CMOS integrated circuits Imaging Logic gates Instruments Transmission line measurements CMOS technology readout circuit CMOS terahertz imaging continuous wave terahertz sensor terahertz detector
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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