NDLI: A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Jenlung Liu Sehyung Jeon Tae-Kwang Jang Dohyung Kim Jihyun Kim Jaejin Park Hojin Park
Copyright Year	2011
Description	Author affiliation: Samsung Electronics. Co. Ltd Yong-in city, South Korea (Jenlung Liu; Sehyung Jeon; Tae-Kwang Jang; Dohyung Kim; Jihyun Kim; Jaejin Park; Hojin Park)
Abstract	A low-voltage operation, small-die-area, fully integrated Phase-Locked Loop (PLL) as a clock generator is described in an advanced 32nm CMOS technology. The PLL employs a fully digital, 6-bit automatic frequency calibrator (AFC), and varactors for frequency fine-tuning. To improve the performance and lower down the cost in mobile SoC applications, the PLL is capable of operating at a supply voltage of 0.8V over production test with only regular threshold voltage (RVT) transistors. The power consumption is measured at 0.7mW when a VCO oscillates at 700MHz frequency under a supply voltage of 0.8V. The total die size is 200μm by 200μm, including global power/ground routing, input ESD cells and on-chip power decoupling capacitors. Production tests show that the PLL consumes less than 0.7mW with a 0.8V supply and rms period jitter is less than 3.3ps at an output frequency of 700MHz.
Starting Page	337
Ending Page	340
File Size	563314
Page Count	4
File Format	PDF
ISBN	9781457717840
e-ISBN	9781457717857
DOI	10.1109/ASSCC.2011.6123582
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-14
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Frequency control Voltage control Voltage-controlled oscillators Jitter Clocks automatic frequency calibrator (AFC) Phase-Locked Loop (PLL) Clock Generator varactor-tuning
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Sub-1V, 1.6mW, 2.06GHz clock generator for mobile SoC applications in 32nm CMOS

A Fast automatic frequency calibration (AFC) scheme for phase-locked loop (PLL) frequency synthesizer

A low-jitter and low-power clock generator

A 62MHz~316MHz Phase-Locked Loop Based on Ring Oscillator for ADC Clock Generator in 0.18m CMOS

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

Study of CMOS voltage controlled oscillator design

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing

Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS

Similar Documents

A Sub-1V, 1.6mW, 2.06GHz clock generator for mobile SoC applications in 32nm CMOS

A Fast automatic frequency calibration (AFC) scheme for phase-locked loop (PLL) frequency synthesizer

A low-jitter and low-power clock generator

A 62MHz~316MHz Phase-Locked Loop Based on Ring Oscillator for ADC Clock Generator in 0.18m CMOS

A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator

Study of CMOS voltage controlled oscillator design

An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing

Adaptive-Bandwidth Phase-Locked Loop With Continuous Background Frequency Calibration

A 0.8V, sub-mW, varactor-tuning ring-oscillator-based clock generator in 32nm CMOS