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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

General chair message

A note from the program chairs

Organizing committee

Steering committee

Program committee

External reviewers

Table of contents

Regular papers [breaker page]

Automated synthesis of FPGA-based heterogeneous interconnect topologies

Generating infrastructure for FPGA-accelerated applications

The power of communication: Energy-efficient NOCS for FPGAS

Altering LUT configuration for wear-out mitigation of FPGA-mapped designs

Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation

Defect-robust FPGA architectures for intellectual property cores in system LSI

Accelerating Random Forest training process using FPGA

FPGA-based K-means clustering using tree-based data structures

Accelerating maximum likelihood estimation for Hawkes point processes

Titan: Enabling large and complex benchmarks in academic CAD

RIFFA 2.0: A reusable integration framework for FPGA accelerators

In pursuit of instant gratification for FPGA design

A fully pipelined FPGA architecture for stochastic simulation of chemical systems

A hardware accelerated approach for imaging flow cytometry

Accelerating solvers for global atmospheric equations through mixed-precision data flow engine

Charge recycling for power reduction in FPGA interconnect

Impact of hard macro size on FPGA clock rate and place/route time

Should FPGAS abandon the pass-gate?

Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS

Criticality-based routing for FPGAS with reverse body bias switch box architectures

A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGAS

A high-performance overlay architecture for pipelined execution of data flow graphs

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS

An efficient FPGA overlay for portable custom instruction set extensions

A packet classifier using LUT cascades based on EVMDDS (k)

Memory efficient IP lookup in 100 GBPS networks

A flexible hash table design for 10GBPS key-value stores on FPGAS

Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS

Optimizing under abstraction: Using prefetching to improve FPGA performance

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction

A secure coprocessor for database applications

Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communications

FPGA based Rekeying for cryptographic key management in Storage Area Network

A FPGA design for high speed feature extraction from a compressed measurement stream

FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source

Scalable and high throughput biosensing platform

Efficient floating-point polynomial evaluation on FPGAS

Iterative floating point computation using FPGA DSP blocks

Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controller

Accelerated FPGA repair through shifted scrubbing

Hardware-accelerated regular expression matching for high-throughput text analytics

Token-based dictionary pattern matching for text analytics

Low-cost, high-performance branch predictors for soft processors

TputCache: High-frequency, multi-way cache for high-throughput FPGA applications

Managing the FPGA memory wall: Custom computing or vector processing?

Rapid FPGA design prototyping through preservation of system logic: A case study

Dynamic branch prediction for high-level synthesis

High-level synthesis with behavioral level multi-cycle path analysis

Simulation-based HW/SW co-debugging for field-programmable systems-on-chip

Multiple constant multiplication with ternary adders

Arithmetic core generation using bit heaps

Energy efficient parameterized FFT architecture

Area/performance evaluation of digit-digit $GF(2^{K})$ multipliers on FPGAS

Short papers (Poster sessions)

A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm

Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS

Bambu: A modular framework for the high level synthesis of memory-intensive applications

A scalable design approach for stencil computation on reconfigurable clusters

Comparing and combining GPU and FPGA accelerators in an image processing context

TILT: A multithreaded VLIW soft processor family

FPGA based hardware-software co-designed dynamic binary translation system

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function

A hardware security scheme for RRAM-based FPGA

Accurate and flexible flow-based monitoring for high-speed networks

A high-performance IPV6 lookup engine on FPGA

High performance architecture for object detection in streamed videos

FPGA-accelerated sliding window classifier with structured features

Performance evaluation of Sparse Matrix-Matrix Multiplication

Aging-based leakage energy reduction in FPGAs

A novel net-partition-based multithread FPGA routing method

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization

Timing-constrained minimum area/power FPGA memory mapping

Shadow And-Inverter Cones

Analyzing the thermal hotspots in FPGA-based embedded systems

Energy efficient architecture for matrix multiplication on FPGAs

An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs

An open-source multi-FPGA modular system for fair benchmarking of True Random Number Generators

Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration

Compact implementation of CCM and GCM modes of AES using DSP blocks

Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

A single-precision compressive sensing signal reconstruction engine on FPGAs

The study of three-dimensional multiphase-flow simulator

Weasel: A platform-independent streaming-optimized SATA controller

A variation-adaptive retiming method exploiting reconfigurability

An event-based middleware for the remote management of runtime hardware reconfiguration

Timing driven RTL-to-RTL partitioner for multi-FPGA systems

Shared memory heterogeneous computation on PCIe-supported platforms

A resource-efficient probabilistic fault simulator

Generation of multi-core systems from multithreaded software

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)

On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)

Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systems

A CMOS Field Programmable Analog Array for intelligent sensory application

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic

Fast dynamically updatable packet classifier on FPGA

A digital architecture for real-time nonuniformity correction of infrared focal-plane arrays

Binarization based implementation for real-time human detection

Magnitude modulation on reconfigurable computing devices

Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD

An automatic FPGA design and implementation framework

A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA

Towards a many-core architecture for HPC

Aging monitoring with local sensors in FPGA-based designs

Runtime assertions and exceptions for streaming systems

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs

A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio

SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems

Design and FPGA implementation of a 100 Gbit/s optical transport network processor

A high performance deblocking filter hardware for High Efficiency Video Coding

Image recognition operation on a dynamically reconfigurable vison architecture

Analysis of matrix multiplication on high density Virtex-7 FPGA

FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family

FEMIP: A high performance FPGA-based features extractor & matcher for space applications

Short papers (PhD forum)

Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimation

A dataflow-inspired CGRA for streaming applications

FPGA based control for real time systems

Pipelining computing stages in configurable multicore architectures

Integration of a multi-FPGA system in a common cluster environment

A space/time tradeoff methodology using higher-order functions

Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview)

Identifying sequences of optimizations for HW/SW compilation

A reconfigurable computing architecture using magnetic tunneling junction memories

Distributed embedded systems design using Petri nets

Short papers (Demonstrations)

Hybrid FPGA-accelerated SQL query processing

Rapid modular assembly of Xilinx FPGA designs

Remote FPGA design through eDiViDe — European Digital Virtual Design Lab

High performance FPGA object detector: Hardware prototype

MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis

NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract

Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs

From Quartus to VPR: Converting HDL to BLIF with the Titan flow

The HercuLeS high-level synthesis environment

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

A spiking neural network on a portable FPGA tablet

A 64-bit MIPS processor running freebsd on a portable FPGA tablet

A self-adaptive image processing application based on evolvable and scalable hardware

SimXMD: Simulation-based HW/SW co-debugging

IOPT-tools — A Web based tool framework for embedded systems controller development using Petri nets

Building partial systems with GoAhead

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in