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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay

An acceleration of a graph cut segmentation with FPGA

An FPGA acceleration of a level set segmentation method

A high performance, open source SATA2 core

IP-XACT extensions for IP interoperability guarantees and software model generation

K-means implementation on FPGA for high-dimensional data using triangle inequality

Enhancing performance of Tall-Skinny QR factorization using FPGAs

Real-time corner and polygon detection system on FPGA

Deep-pipelined FPGA implementation of ellipse estimation for eye tracking

A Benign Hardware Trojan on FPGA-based embedded systems

Breaking the GSM A5/1 cryptography algorithm with rainbow tables and high-end FPGAS

On reconfigurable fabrics and generic side-channel countermeasures

Hardware implementation of stereo correspondence algorithm for the ExoMars mission

Design space exploration for automatically generated cryptographic hardware using functional languages

Fast and accurate Single Bit Error injection into SRAM Based FPGAs

$(GECO)^{2}:$ A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture

Design and implementation of fault-tolerant soft processors on FPGAs

Towards GCC-based automatic soft-core customization

An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals

Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

ITester: A FPGA based high performance traffic replay tool

Modeling and synthesis of a Dynamic and Partial Reconfiguration controller

An open-source design and validation platform for reconfigurable systems

Floating point HOG implementation for real-time multiple object detection

Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit

A high performance and low energy intra prediction hardware for High Efficiency Video Coding

High-level linear projection circuit design optimization framework for FPGAs under over-clocking

Evaluating the efficiency of DSP Block synthesis inference from flow graphs

System#: High-level synthesis of physical simulations for FPGA-based real-time execution

Bil: A tool-chain for bitstream reverse-engineering

A region merging approach for image segmentation on FPGA

On measurement of impact of the metallization and FPGA design to the changes of slice parameters and generation of delay faults

Industrial sessions

Dataflow supercomputing

Invited paper: Using OpenCL to evaluate the efficiency of CPUS, GPUS and FPGAS for information filtering

Dataflow supercomputing

A resiliency-aware scheduling approach for FPGA configuration: Preliminary results

Power/performance optimization in FPGA-based asymmetric multi-core systems

Thermal-aware partitioning for 3D FPGAs

Reconfigurable multi-processor architecture for streaming applications

NoC-AXI interface for FPGA-based MPSoC platforms

Modeling of dynamic reconfigurable systems with Haskell

Stimulation board for automated verification of touchscreen-based devices

High level structural description of streaming applications

Ambient hardware and the case for transcoding media streams

Combining data and computation transformations for fine-grain reconfigurable architectures

Implementation and outcomes of FPGA-based system design in Mongolian education

Welcome to FPL2012

Hardware implementation of MRF map inference on an FPGA platform

CAAD BLASTP 2.0: NCBI BLASTP accelerated with pipelined filters

Polyblaze: From one to many bringing the microblaze into the multicore era with Linux SMP support

Automating the design of mLUT MPSoPC FPGAs in the cloud

A scalable complex event processing framework for combination of SQL-based continuous queries and C/C++ functions

Hardware implementation of motion blur removal

Correctly rounded floating-point division for DSP-enabled FPGAs

Reduced complexity single and multiple constant multiplication in floating point precision

FPGA-based design and implementation of a multi-GBPS LDPC decoder

Optimizing packet lookup in time and space on FPGA

Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems

High-level aging estimation for FPGA-mapped designs

Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments

Overhead and reliability analysis of algorithm-based fault tolerance in FPGA systems

Automatically exploiting regularity in applications to reduce reconfiguration memory requirements

Mapping logic to reconfigurable FPGA routing

Maximizing the reuse of routing resources in a reconfiguration-aware connection router

Random decision tree body part recognition using FPGAs

Acceleration of distance-to-default with hardware-software co-design

An efficient hardware architecture of the optimised SIFT descriptor generation

Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array

A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function

Non-volatile 3D stacking RRAM-based FPGA

Intra-chip physical parameter sensor for FPGAS using flip-flop metastability

A novel microprocessor-intrinsic Physical Unclonable Function

FPGA based key generation technique for anti-counterfeiting methods using Physically Unclonable Functions and artificial intelligence

Technical program

Dynamic multiobjective optimization management of the Energy-Performance-Accuracy space for separable 2-D complex filters

HCM: An abstraction layer for seamless programming of DPR FPGA

Early performance estimation of image compression methods on soft processors

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system

Sliding block Viterbi decoders in FPGA

Dynamic query switching for complex event processing on FPGAs

Dual-core motion estimation processor

On the automatic integration of hardware accelerators into FPGA-based embedded systems

Design of a novel Quantum-dot Cellular Automata Field Programmable Gate Array

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture

DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler

Low area memory-free FPGA implementation of the AES algorithm

An adaptive FPGA implementation of multi-core K-nearest neighbour ensemble classifier using dynamic partial reconfiguration

Fast digital rendering for special effects

Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs

A new self-adapting architecture for feature detection

Custom instructions with local memory elements without expensive DMA transfers

Dual MicroBlaze rekeying processor for group key management

Lightweight reconfiguration security services for AXI-based MPSoCs

Examination of the concept of a row-column separated median filter

Detecting power attacks on reconfigurable hardware

Efficient and side-channel-secure block cipher implementation with custom instructions on FPGA

CRUSH: Cognitive Radio Universal Software Hardware

Data coding functions for Software Defined Radios implemented on R3TOS

EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip

Limitations of incremental signal-tracing for FPGA debug

SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

FPGAs for trusted cloud computing

Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs

Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources

On the difficulty of pin-to-wire routing in FPGAs

Routing algorithms for FPGAS with sparse intra-cluster routing crossbars

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study

Bio-inspired walking: A FPGA multicore system for a legged robot

A scalable FPGA-based design for field programmable large-scale ion channel simulations

Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation

FPGA based acceleration of computational fluid flow simulation on unstructured mesh geometry

Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics

Analytical placement for heterogeneous FPGAs

Profiling FPGA floor-planning effects on timing closure

Multi-kernel floorplanning for enhanced CGRAS

Optimising explicit finite difference option pricing for dynamic constant reconfiguration

Exploiting run-time reconfiguration in stencil computation

A two step hardware design method using CλaSH

Convey vector personalities - FPGA acceleration with an openmp-like programming effort?

Improving memory support in the VTR flow

Verification of streaming designs by combining symbolic simulation and equivalence checking

Academic and industrial workshops

CaaS: Core as a service realizing hardware sercices on reconfigurable MPSoCS

Hardware acceleration and data-utility improvement for low-latency privacy preserving mechanism

Dataflow graph partitioning for high level synthesis

A fast and high quality stereo matching algorithm on FPGA

An FPGA aligner for short read mapping

Raising the abstraction level of HDL for control-dominant applications

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification

Speedy bus mastering PCI express

Adaptive Sequential Monte Carlo approach for real-time applications

From opencl to high-performance hardware on FPGAS

A framework for Open Tiled Manycore System-On-Chip

Fault detection and avoidance of FPGA in various granularities

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration

Development of an FPGA-based real-time P300 speller

Influence of operating conditions on ring oscillator-based entropy sources in FPGAs

Exploration of ring oscillator design space for temperature measurements on FPGAs

Extending BORPH for shared memory reconfigurable computers

Automatic generation of application-specific accelerators for FPGAs from python loop nests

PPMC: Hardware scheduling and memory management support for multi accelerators

Performance analysis of fully-adaptable CRC accelerators on an FPGA

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in