NDLI: Preface

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

[Front and back covers]

Organizing committee

Program committee

Steering committee

Additional reviewers

Table of contents

Customizable domain-specific computing

In search of agile hardware

The evolution of architecture exploration of programmable devices

FPGA challenges and opportunities at 40nm and beyond

Virtex-6 and Spartan-6, plus a look into the future

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link

Hardware implementation of MPI_Barrier on an FPGA cluster

Fast critical sections via thread scheduling for FPGA-based multithreaded processors

A biophysically accurate floating point somatic neuroprocessor

CNP: An FPGA-based processor for Convolutional Networks

Noise impact of single-event upsets on an FPGA-based digital filter

Compiler assisted runtime task scheduling on a reconfigurable computer

Data parallel FPGA workloads: Software versus hardware

Generating high-performance custom floating-point pipelines

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

Exploring reconfigurable architectures for explicit finite difference option pricing models

Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming

A runtime relocation based workflow for self dynamic reconfigurable systems design

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

FPGA partial reconfiguration via configuration scrubbing

Improving logic density through synthesis-inspired architecture

Clock gating architectures for FPGA power reduction

Program-driven fine-grained power management for the reconfigurable mesh

Performance comparison of FPGA, GPU and CPU in image processing

Self-organizing multi-cue fusion for FPGA-based embedded imaging

Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation

An analytical model relating FPGA architecture and place and route runtime

Replace: An incremental placement algorithm for field programmable gate arrays

Optimal runtime reconfiguration strategies for systolic arrays

A multi-FPGA architecture for stochastic Restricted Boltzmann Machines

Comparing fine-grained performance on the Ambric MPPA against an FPGA

Low power techniques for Motion Estimation hardware

Building heterogeneous reconfigurable systems using threads

Bitstream compression through frame removal and partial reconfiguration

Operation scheduling for FPGA-based reconfigurable computers

FPGA-accelerated retinal vessel-tree extraction

Novel strategies for hardware acceleration of frequent itemset mining with the apriori algorithm

Reconfiguration-based time-to-digital converter for Virtex FPGAs

An efficient reconfigurable architecture to implement dense stereo vision algorithm using high-level synthesis

High speed fixed point dividers for FPGAs

A self-reconfiguring architecture supporting multiple objective functions in genetic algorithms

Automatic generation of FPGA hardware accelerators using a domain specific language

A dynamically reconfigurable parallel pixel processing system

An approach to system-wide fault tolerance for FPGAs

A multi-layered XML schema and design tool for reusing and integrating FPGA IP

Dynamic Polymorphic Reconfiguration for anti-tamper circuits

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model

Run-time Partial Reconfiguration speed investigation and architectural design space exploration

Dynamic reconfigurable mixed-signal architecture for safety critical applications

Using 3D integration technology to realize multi-context FPGAs

Mems optically reconfigurable gate array

Sharf: An FPGA-based customizable processor architecture

Multigigabit network traffic processing

Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors

Rapid design exploration framework for application-aware customization of soft core processors

Hot-Swapping architecture extension for mitigation of permanent functional unit faults

SVM speaker verification system based on a low-cost FPGA

An FPGA-based embedded wideband audio codec system

A novel states recovery technique for the TMR softcore processor

Performance metrics for hybrid multi-tasking systems

Cooperative multithreading in dynamically reconfigurable systems

The educational processor Sweet-16

Secure FPGA technologies and techniques

FPGA supercomputing platforms: A survey

A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs

Run-time resource management in fault-tolerant network on reconfigurable chips

Off-line placement of hardware tasks on FPGA

An FPGA based verification platform for HyperTransport 3.x

A virus scanning engine using a parallel finite-input memory machine and MPUs

Tracking elephant flows in internet backbone traffic with an FPGA-based cache

Proteus: An architectural synthesis tool based on the stream programming paradigm

Binary Synthesis with multiple memory banks targeting array references

Mapping basic prefix computations to fast carry-chain structures

FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic

Compensating for variability in FPGAs by re-mapping and re-placement

Synthesis of the SR programming language for complex FPGAs

Exploiting synchronous placement for asynchronous circuits onto commercial FPGAs

Using C-to-gates to program streaming image processing kernels efficiently on FPGAs

A reconfigurable FIR/FFT unit for wireless telecommunication systems

A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM)

Enhanced gradient-based motion vector coprocessor

Dynamic reconfiguration system for real-time video processing

Numerically controlled oscillators using linear approximation

Random numbers generation: Investigation of narrowtransitions suppression on FPGA

Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators

CREMA: A coarse-grain reconfigurable array with mapping adaptiveness

Efficient AES S-boxes implementation for non-volatile FPGAs

Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs

Compact FPGA implementation of Camellia

FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture

An FPGA design for evaluating score function in protein energy calculation

Emulating Spiking Neural Networks for edge detection on FPGA hardware

A reconfigurable architecture for the Phylogenetic Likelihood Function

Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator

High-level programming of coarse-grained reconfigurable architectures

FPGA support for satellite computations of hyper spectral images

Improving the memory footprint and runtime scalability of FPGA CAD algorithms

Efficient techniques and methodologies for embedded system design usign free hardware and open standards

Multi-terminal BDD synthesis and applications

Soft errors in Flash-based FPGAs: Analysis methodologies and first results

RISPP: A run-time adaptive reconfigurable embedded processor

Coarse-grained dynamically reconfigurable architecture with flexible reliability

A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support

Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space

Modeling post-techmapping and post-clustering FPGA circuit depth

Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems

An ASIC perspective on FPGA optimizations

Recursion in reconfigurable computing: A survey of implementation approaches

A comparison of FPGA and FPAA technologies for a signal processing application

A radix-8 complex divider for FPGA implementation

Exploiting fast carry-chains of FPGAs for designing compressor trees

Large multipliers with fewer DSP blocks

Area estimation and optimisation of FPGA routing fabrics

In field, energy-performance tunable FPGA architectures

Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays

A fast parallel matrix multiplication reconfigurable unit utilized in face recognitions systems

Design space exploration of reconfigurable systems for calculating flying object's optimal noise reduction paths

Real-time processing of local contrast enhancement on FPGA

Enhancements to FPGA design methodology using streaming

General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems

Optimising designs by combining model-based and pattern-based transformations

sFPGA2 - A scalable GALS FPGA architecture and design methodology

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol

A new deadlock-free fault-tolerant routing algorithm for NoC interconnections

Accelerating HMMER search using FPGA

An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure

Efficient particle-pair filtering for acceleration of molecular dynamics simulation

Implementation of a reconfigurable Fast Fourier Transform application to digital terrestrial television broadcasting

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes

A highly scalable Restricted Boltzmann Machine FPGA implementation

Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA

Clock duplicity for high-precision timestamping in Gigabit Ethernet

DPA resistance for light-weight implementations of cryptographic algorithms on FPGAs

Increasing stability and distinguishability of the digital fingerprint in FPGAs through input word analysis

Towards a unique FPGA-based identification circuit using process variations

IP protection in Partially Reconfigurable FPGAs

FPGA accelerating three QR decomposition algorithms in the unified pipelined framework

FPGA-accelerated Information Retrieval: High-efficiency document filtering

A toolset for the analysis and optimization of motion estimation algorithms and processors

Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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