NDLI: Searching for ET with FPGA’S

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

Table of contents

FPGA: The future platform for transforming, transporting and computing data

FPGAS in high energy physics experiments at CERN

Searching for ET with FPGA’S

Keynote: High performance computing based on FPGAS

Increasing the level of abstraction in FPGA-based designs

Modeling recursion data structures for FPGA-based implementation

A portable abstraction layer for hardware threads

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems

Three-stage pipeline implementation for SHA2 using data forwarding

Chosen-message SPA attacks against FPGA-based RSA hardware implementations

Exploring FPGA network on chip implementations across various application and network loads

Reducing interconnection cost in coarse-grained dynamic computing through multistage network

NOC architecture design for multi-cluster chips

Fast and accurate resource estimation of RTL-based designs targeting FPGAS

Fast toggle rate computation for FPGA circuits

On-the-fly attestation of reconfigurable hardware

How fast is an FPGA in image processing?

A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays

Real-time image super resolution using an FPGA

sFPGA — A scalable switch based FPGA architecture and design methodology

FPGA family composition and effects of specialized blocks

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS

No-break dynamic defragmentation of reconfigurable devices

ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS

An efficient run-time router for connecting modules in FPGAS

High-speed regular expression matching engine using multi-character NFA

Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Mining Association Rules with systolic trees

A configurable and programmable motion estimation processor for the H.264 video codec

A flexible and reliable embedded system for detector control in a high energy physics experiment

Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic

Loop unrolling and shifting for reconfigurable architectures

CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework

FPGA implementation of a flexible decoder for long LDPC codes

Towards an “early neural circuit simulator”: A FPGA implementation of processing in the rat whisker system

Decimal multiplier on FPGA using embedded binary multipliers

A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor

Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor

Instruction buffer mode for multi-context Dynamically Reconfigurable Processors

An analytical model describing the relationships between logic architecture and FPGA density

Rapid estimation of power consumption for hybrid FPGAs

A technique for minimizing power during FPGA placement

Sampling from the exponential distribution using independent Bernoulli variates

Enhancing security of ring oscillator-based trng implemented in FPGA

Digital hilbert transformers for FPGA-based phase-locked loops

Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip

GICS: Generic interconnection system

A link removal methodology for Networks-on-Chip on reconfigurable systems

Mapping and scheduling with task clustering for heterogeneous computing systems

Low-latency high-bandwidth HW/SW communication in a virtual memory environment

ATCA-based computation platform for data acquisition and triggering in particle physics experiments

An FPGA-based high-speed, low-latency trigger processor for high-energy physics

Shared reconfigurable architectures for CMPS

Power reduction techniques for Dynamically Reconfigurable Processor Arrays

An integrated debugging environment for FPGA computing platforms

Secure FPGA configuration architecture preventing system downgrade

Bitstream compression techniques for Virtex 4 FPGAs

FPGA acceleration of Monte-Carlo based credit derivative pricing

FPGA acceleration of quasi-Monte Carlo in finance

Acceleration of a production rigid molecule docking code

SPP1148 booth: Fine grain reconfigurable architectures

SPP1148 booth: Coarse-grained reconfiguration

SPP1148 booth: Application-specific reconfigurable processors

SPP1148 booth: Seamless design flow for reconfigurable systems

SPP1148 booth: Network processors

SPP1148 booth: Hyperreconfigurable architectures

Foreword DFG SPP1148 session

Floating point datapath synthesis for FPGAs

Automatic generation of run-time parameterizable configurations

Generation of partial FPGA configurations at run-time

Novel FPGA based Haar classifier face detection algorithm acceleration

An FPGA-based implementation of the MINRES algorithm

Efficient FPGA mapping of Gilbert’s algorithm for SVM training on large-scale classification problems

Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures

An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation

Memory access parallelisation in high-level language compilation for reconfigurable adaptive computers

Reconfigurable hardware: The holy grail of matching performance with programming productivity

Fault tolerant methods for reliability in FPGAs

A non-volatile run-time FPGA using thermally assisted switching MRAMS

The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays

An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture

EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs

The hardware application platform of the hartes project

Scalable high performance computing on FPGA clusters using message passing

FPGA interconnect design using logical effort

An ILP formulation for architectural synthesis and application mapping on FPGA-based hybrid multi-processor SOC

Operating system support for online partial dynamic reconfiguration management

Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory

Numerical function generators using bilinear interpolation

A versatile hardware architecture for a CFAR detector based on a linear insertion sorter

Polymorphic wavelet architectures using reconfigurable hardware

Direct sigma-delta modulated signal processing in FPGA

A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor

Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks

A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck

Customized Reconfigurable Interconnection Networks for multiple application SOCS

New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability — the RAMPSoC approach

CVC: The C to RTL compiler for callback-based verification model

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS

SAT-based resource binding for reducing critical path delays

BOUNCE, a new approach to measure sub-nanosecond time intervals

Power efficient DSP datapath configuration methodology for FPGA

IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration

An FPGA architecture for the Pagerank eigenvector problem

Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems

Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC

Exploring compact design on high throughput coarse grained reconfigurable architectures

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor

A new methodology for debugging and validation of soft cores

Convergence analysis of run-time distributed optimization on adaptive systems using game theory

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation

Parallel hardware objects for dynamically partial reconfiguration

File system access from reconfigurable FPGA hardware processes in BORPH

Self-recofigurable embedded systems on Spartan-3

An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor

Creating unique identifiers on field programmable gate arrays using natural processing variations

Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA

A comparison of embedded reconfigurable video-processing architectures

Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor

Cluster architecture based on low cost reconfigurable hardware

A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA

Comparing throughput and power consumption in both sequential and reconfigurable processors

Data path driven waveform-like reconfiguration

Active kernel monitoring to combat scheduler gaming in reconfigurable computing systems

An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects

A hardware compilation flow for instance-specific VLIW cores

A reconfigurable accelerator for quantum computations

High-performance fpga-based floating-point adder with three inputs

A rate-based prefiltering approach to blast acceleration

Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration

Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching

A low overhead fault tolerant FPGA with new connection box

An optimization method of DMA transfer for a general purpose reconfigurable machine

Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform

Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs

A dynamic temperature control simulation system for FPGAs

Practical implementation of a network-based stochastic biochemical simulation system on an FPGA

Compiled hardware acceleration of Molecular Dynamics code

Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS

Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis

Connected components analysis of streamed images

On the design parameters of runtime reconfigurable systems

Teaching FPGA system design via a remote laboratory facility

Towards benchmarking energy efficiency of reconfigurable architectures

FPGA interconnect sizing using extended logical effort model

Bio-inspiration helps computers: A new machine

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

Thermal aware FPGA architectures and CAD

Combating process variation on FPGAS with a precise at-speed delay measurement method

Adaptive precision technique for genetic algorithms

Reconfigurable many-cores with lean interconnect

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

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