NDLI: Clock-Aware Placement for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Lamoureux, J. Wilton, S.J.E.
Copyright Year	2007
Description	Author affiliation: Univ. of British Columbia, Vancouver (Lamoureux, J.; Wilton, S.J.E.)
Abstract	The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of power, since it connects to every latch on the FPGA and toggles every cycle, but the design of the clock network also affects how efficiently the rest of the application can be implemented since it imposes constraints on the CAD tools which map the application onto the FPGA. To examine this tradeoff, this paper describes and compares new clock-aware placement techniques and then examines how the clock network architecture affects overall power, area, and delay. Our results show that the placement techniques used to make placement clock-aware have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the clock network architecture is also important. On average, FPGAs with an efficient clock network were up to 12.5% more energy efficient and 7.2% faster than other FPGAs.
Starting Page	124
Ending Page	131
File Size	4581306
Page Count	8
File Format	PDF
ISBN	9781424410590
DOI	10.1109/FPL.2007.4380636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-27
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Field programmable gate arrays Design automation Latches Circuits Costs Delay Energy efficiency Technological innovation System-level design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Architecture and CAD for FPGA Clock Networks

Clock-Gating in FPGAs: A Novel and Comparative Evaluation

Replace: An incremental placement algorithm for field programmable gate arrays

Latch-Based Performance Optimization for FPGAs

Duty cycle aware application design using FPGAs

A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs

Latch-Based Performance Optimization for Field-Programmable Gate Arrays

Robust Optimization of Multiple Timing Constraints

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

Clock-Aware Placement for FPGAs

Similar Documents

Architecture and CAD for FPGA Clock Networks

Clock-Gating in FPGAs: A Novel and Comparative Evaluation

Replace: An incremental placement algorithm for field programmable gate arrays

Latch-Based Performance Optimization for FPGAs

Duty cycle aware application design using FPGAs

A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs

Latch-Based Performance Optimization for Field-Programmable Gate Arrays

Robust Optimization of Multiple Timing Constraints

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

Clock-Aware Placement for FPGAs