NDLI: Improved power supply noise control for pseudo functional test

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2015 IEEE 33rd VLSI Test Symposium (VTS)

2014 IEEE 32nd VLSI Test Symposium (VTS)

Organizing committee

Steering and program committees

Acknowledgments

VTS 2013 Best Paper Award [includes 2 other awards]

TTTC: Test technology technical council

Fault simulation with test switching for static test compaction

Fast evaluation of test vector sets using a simulation-based statistical metric

Improving CMOS open defect coverage using hazard activated tests

Efficient Monte Carlo-based analog parametric fault modelling

A method for phase noise extraction from data communication

Accurate and efficient method of jitter and noise separation and its application to ADC testing

Innovative practices session 1C: Existing/emerging low power techniques

Testing methods for a write-assist disturbance-free dual-port SRAM

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells

Fault modeling and test algorithm creation strategy for FinFET-based memories

New topic session 2B: Co-design and reliability of power electronic modules — Current status and future challenges

Innovative practices session 2C: Advanced in yield learning

A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters

Alternative “safe” test of hysteretic power converters

Accelerating capture of infrequent errors on ATE for silicon TV tuners

Self-heating thermal-aware testing of FPGAs

Structural Software-Based Self-Test of Network-on-Chip

Accelerated online error detection in many-core microprocessor architectures

Innovative practices session 3C: Solving today's test challenges

Special session 4A: Elevator talks

Special session 4B: Panel: Testing and calibration for power management circuits

Innovative practices session 4C: Disruptive solutions in the non-digital world

Test generation and design-for-testability for flow-based mVLSI microfluidic biochips

Fault tolerant nanoarray circuits: Automatic design and verification

Detection, diagnosis, and repair of faults in memristor-based memories

Quality versus cost analysis for 3D Stacked ICs

Test planning and test access mechanism design for stacked chips using ILP

Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking

Innovative practices session 5C: Machine learning and data analysis in test

SMV methodology enhancements for high speed I/O links of SoCs

Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithms

Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements

At-speed interconnect testing and test-path optimization for 2.5D ICs

Built-in self-test for manufacturing TSV defects before bonding

TSV aware timing analysis and diagnosis in paths with multiple TSVs

Unstructured text: Test analysis techniques applied to non-test problems

Reliability enhancement using in-field monitoring and recovery for RF circuits

Continuous wave radar circuitry testing using OFDM technique

A built-in gain calibration technique for RF low-noise amplifiers

New topic session 7B: Challenges and opportunities in test and design for test (DFT) of MEMS sensors

Innovative practices session 7C: Reduced pin-count testing — How low can we go?

Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final

Special session 8B — Panel: In-field testing of SoC devices: Which solutions by which players?

Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test

Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field tests

Power/ground supply voltage variation-aware delay test pattern generation

Improved power supply noise control for pseudo functional test

Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression

Development and empirical verification of an accuracy model for the power down leakage tests

A 4-GHz universal high-frequency on-chip testing platform for IP validation

Hot topic session 9C: Test and fault tolerance for emerging memory technologies

A shared memory based parallel diagnosis system

An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model

Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuits

Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements

Active defense against counterfeiting attacks through robust antifuse-based on-chip locks

Auto-identification of positive feedback loops in multi-state vulnerable circuits

Innovative practices session 10C: Advances in DFT and compression

On the use of multi-cycle tests for storage of two-cycle broadside tests

Test-time optimization in NOC-based manycore SOCs using multicast routing

On-chip voltage-droop prediction using support-vector machines

Special session 11B: ITRS adaptive test update

Special session 11C: Young professionals in test — Elevator talks

Hot topic session 12A: Split manufacturing — IARPA's TIC program

Hot topic session 12B: Stay relevant with standards-based DFT

Special session 12C: Young professionals in test — Town meeting

2013 IEEE 31st VLSI Test Symposium (VTS)

2012 IEEE 30th VLSI Test Symposium (VTS)

29th VLSI Test Symposium

2010 28th VLSI Test Symposium (VTS)

2009 27th IEEE VLSI Test Symposium

26th IEEE VLSI Test Symposium (vts 2008)

25th IEEE VLSI Test Symposium (VTS'07)

24th IEEE VLSI Test Symposium

23rd IEEE VLSI Test Symposium (VTS'05)

22nd IEEE VLSI Test Symposium, 2004. Proceedings.

Proceedings. 21st VLSI Test Symposium, 2003.

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

Proceedings 18th IEEE VLSI Test Symposium

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

Proceedings of 14th VLSI Test Symposium

Proceedings 13th IEEE VLSI Test Symposium

Proceedings of IEEE VLSI Test Symposium

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

Digest of Papers. 1992 IEEE VLSI Test Symposium

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

Improved power supply noise control for pseudo functional test

Content Provider	IEEE Xplore Digital Library
Author	Tengteng Zhang Walker, D.M.H.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Texas A&M Univ., College Station, TX, USA (Tengteng Zhang; Walker, D.M.H.)
Abstract	Differences in power supply noise (PSN) between functional and structural delay testing can lead to differences in chip operating frequencies of 30% or more. High delay correlation between structural and functional test requires the paths under test to experience the worst-case realistic PSN. We present a PSN control method for pseudo functional test that combines random flipping and background patterns to efficiently fill don't care bits. Dynamic bit weighting permits intelligent selection of background patterns. Experimental results on benchmark circuits achieve worst-case realistic PSN in significantly less CPU time than prior techniques.
Sponsorship	IEEE Comput. Soc.
Starting Page	1
Ending Page	6
File Size	332623
Page Count	6
File Format	PDF
ISBN	9781479926114
DOI	10.1109/VTS.2014.6818784
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Central Processing Unit Delays Noise Testing Correlation Switches Power supplies pseudo-functional test delay testing power supply noise
Content Type	Text
Resource Type	Article

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