NDLI: Proceedings. 22nd IEEE VLSI Test Symposium

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2015 IEEE 33rd VLSI Test Symposium (VTS)

2014 IEEE 32nd VLSI Test Symposium (VTS)

2013 IEEE 31st VLSI Test Symposium (VTS)

2012 IEEE 30th VLSI Test Symposium (VTS)

29th VLSI Test Symposium

2010 28th VLSI Test Symposium (VTS)

2009 27th IEEE VLSI Test Symposium

26th IEEE VLSI Test Symposium (vts 2008)

25th IEEE VLSI Test Symposium (VTS'07)

24th IEEE VLSI Test Symposium

23rd IEEE VLSI Test Symposium (VTS'05)

22nd IEEE VLSI Test Symposium, 2004. Proceedings.

Proceedings. 22nd IEEE VLSI Test Symposium

Proceedings 22 nd IEEE VLSI Test Symposium

Proceedings 22 nd IEEE VLSI Test Symposium Copyright Page

Proceedings 22nd IEEE VLSI Test Symposium Table of contents

Steering Committee

Program committee

Acknowledgements

TTTC: Test Technology Technical Council

Test technology educational program TTEP 2004 overview of tutorials of VTS 2004

When digital becomes analog - Interfaces in high speed test

Infrastructure IP for SOC

Memory test and self-test for deep sub-micron technologies

Statistical methods for VLSI test, quality and reliability

VTS 2003 best panel award

VTS 2003 best innovative practice session award

Excitation, observation, and ELF-MD: optimization criteria for high quality test sets

ELF-Murphy data on defects and tests sets

An experimental study of N-detect scan ATPG patterns on a processor

Robust testing a subset of paths - untested paths in the circuit

A statistical fault coverage metric for realistic path delay faults

Delay defect screening using process monitor structures

Built-in current sensor for /spl Delta/I/sub DDQ/ testing of deep submicron digital CMOS ICs

On new current signatures and adaptive test technique combination

On comparison of NCR effectiveness with a reduced I/sub DDQ/ vector set

Changing the scan enable during shift

3-stage variable length continuous-flow scan vector decompression scheme

Generating At-Speed array fail maps with low-speed ATE

Razor: a tool for post-silicon scan ATPG pattern debug and its application

Yield analysis of logic circuits

FPGA bridging fault detection and location via differential I/sub DDQ/

Effects of bit line coupling on the faulty behavior of DRAMs

New test methodology for resistive open defect detection in memory address decoders

March iC-: an improved version of March C- for ADOFs detection

Multi-modal built-in self-test for symmetric microsystems

A dual-mode built-in self-test technique for capacitive MEMS devices

A multi-configuration strategy for an application dependent testing of FPGAs

The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults

Sensing temperature in CMOS circuits for thermal testing

Detection of temperature sensitive defects using ZTC

Planar high performance ring generators

Logic BIST using constrained scan cells

BIST technique by equally spaced test vector sequences

Wafer-level RF test and DfT for VCO modulating transceiver architectures

GHz RF front-end bandwidth time domain measurement

System-level testing of RF transmitter specifications using optimized periodic bitstreams

Reducing embedded SRAM test time under redundancy constraints

Memory BIST using ESP

A methodology for design and evaluation of redundancy allocation algorithms

An on-chip transfer function characterization system for analog built-in testing

A scalable on-chip jitter extraction technique

Feature extraction based built-in alternate test of RF components using a noise reference

Defects and faults in quantum cellular automata at nano scale

Generalized sensitization using fault tuples

Fault simulation model for i/sub DDT/ testing: an investigation

A diversified memory built-in self-repair approach for nanotechnologies

Cost-driven selection of parity trees

Soft delay error effects in CMOS combinational circuits

Testing systems wirelessly

Design of wireless sub-micron characterization system

Boundary scan for 5-GHz RF pins using LC isolation networks

Hybrid BIST for system-on-a-chip using an embedded FPGA core

Defect-aware SOC test scheduling

Designing reconfigurable multiple scan chains for systems-on-chip

Prediction of analog performance parameters using oscillation based test

An approach to the built-in self-test of field programmable analog arrays

Efficient ATPG for design validation based on partitioned state exploration histories

Proceedings. 21st VLSI Test Symposium, 2003.

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

Proceedings 18th IEEE VLSI Test Symposium

Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)

Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

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Proceedings 13th IEEE VLSI Test Symposium

Proceedings of IEEE VLSI Test Symposium

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium

Digest of Papers. 1992 IEEE VLSI Test Symposium

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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