NDLI: A physics-based compact model of quantum-mechanical effects for thin cylindrical Si-Nanowire MOSFETs

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Table of contents

Has the sun finally risen on photovoltaics?

The future of semiconductor industry - A foundry's perspective

From living faster to living better

Carrier transport and stress engineering in advanced nanoscale MOS transistors

The impact on device characteristics with STI formed by spin-on dielectric in high density NAND flash memory

Properties of very thin adenine layer with high inhibition for 32nm node Cu/Low-K interconnection

Boron carbon nitride film containing hydrogen for 2nm node low-k interconnection

Ge shallow junction formation by As implantation and flash lamp annealing

Impact of lithography variations on advanced CMOS devices

Stress-enhancement technique in narrowing NMOSFETs with damascene-gate process and tensile liner

Additive mobility enhancement and off-state current reduction in SiGe channel pMOSFETs with optimized Si Cap and high-k metal gate stacks

Dopant and thermal interaction on SPE formed SiC for NMOS performance enhancement

Successful integration scheme of cost effective dual embedded stressor featuring carbon implant and solid phase epitaxy for high performance CMOS

An investigation about the limitation of strained-Si technology

Characterization of poly-Silicon emitter BJTs as access devices for Phase Change Memory

Low current and voltage resistive switching memory device using novel Cu/Ta/W structure

A novel Multi - Nitridation ONO interpoly dielectric (MN-ONO) for highly reliable and high performance NAND Flash memory

Forming-free HfO bipolar RRAM device with improved endurance and high speed operation

Multi-level phase change memory using slow-quench operation: GST vs. GSST

The standby power challenge: Wake-up receivers to the rescue

Realizing steep subthreshold swing with Impact Ionization Transistors

Optimizing tunnel FET performance - Impact of device structure, transistor dimensions and choice of material

Nanoelectromechanical systems for ultra-low-power computing and VLSI

Single-Metal Dual-Dielectric (SMDD) gate-first CMOS integration towards low V and high performance

Low capacitance approaches for 22nm generation Cu interconnect

A V tunable Single Metal Single Dielectric approach using As I/I into TiN/HfO for 32nm node and beyond

La-doped metal/high-K nMOSFET for sub-32nm HP and LSTP application

Extending spectroscopic ellipsometry for identification of electrically active defects in Si/SiO/high-k/metal gate stacks

22nm CMOS approaches by PVD TiN or Ti-Silicide as metal gate

Reliability assessment of low |V| metal high-κ gate stacks for high performance applications

High performance metal/insulator/metal capacitors using HfTiO as dielectric

High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge?

Scaling challenges of MOSFET for 32nm node and beyond

p-FinFETs with Al segregated $NiSi/p^{+}-Si$ source/drain contact junction for series resistance reduction

Impacts of NBTI on SRAM array with power gating structure

CMOS technology roadmap projection including parasitic effects

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

Investigation of low frequency noise in uniaxial strained PMOSFETs

FDSOI CMOS with dual backgate control for performance and power modulation

Sub-32nm CMOS technology enhancement for low power applications

Highly performant FDSOI pMOSFETs with metallic source/drain

High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

Double patterning interactions with wafer processing, OPC and physical design flows

Multiple electron beam maskless lithography for high-volume manufacturing

Status and challenges of extreme-UV lithography

Recent developments in NAND flash scaling

Modeling and scaling evaluation of junction-free charge-trapping NAND flash devices

Gate last MOSFET with air spacer and self-aligned contacts for dense memories

A physics-based compact model of quantum-mechanical effects for thin cylindrical Si-Nanowire MOSFETs

A new technique to extract the gate bias dependent s/d series resistance of sub-100nm MOSFETs

Analytical modeling of Accumulation-Mode Suspended-Gate MOSFET and process challenges for very low operating power devices

A new robust non-local algorithm for band-to-band tunneling simulation and its application to Tunnel-FET

Investigation of static noise margin of Ultra-Thin-Body SOI SRAM cells in subthreshold region using analytical solution of poisson's equation

The promise and implementation of three dimensional integration

Optimization of the channel lateral strain profile for improved performance of multi-gate MOSFETs

A novel double-gated nanowire TFT and investigation of its size dependency

Fermi level depinning for the design of III–V FET source/drain contacts

Influence of gate misalignment on the electrical characteristics of MuGFETs

FinFET resistance mitigation through design and process optimization

Sub-100µW low power operation of Vibrating Body FETs

Inversion-channel GaN MOSFET using atomic-layer-deposited Al as gate dielectric

A comparison study of Silicon Nanowire Transistor with Schottky-Barrier source/drain and doped source/drain

High mobility SiGe shell-Si core omega gate pFETS

Metal-oxide-semiconductor devices with UHV-Ga) on Ge(100)

Self-aligned inversion channel InAs N-MOSFETs with ALD-Al and MBE-Al) as gate dielectrics

Inversion-type surface channel InAs metal-oxide-semiconductor field-effect transistors with metal-gate/high-k dielectric stack and CMOS-compatible PdGe contacts

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

Tri-gated poly-Si nanowire SONOS devices

Overall operation considerations for a SONOS-based memory

Reliability study of MANOS with and without a SiO buffer layer and BE-MANOS charge-trapping NAND flash devices

Reliability of planar and FinFET SONOS devices for NAND flash applications - Field enhancement vs. barrier engineering

Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100K cycle endurance

2009 International symposium on VLSI technology, systems and applications organization

2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

2006 International Symposium on VLSI Technology, Systems, and Applications

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications

1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers

1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers

1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers

International Symposium on VLSI Technology, Systems and Applications,

A physics-based compact model of quantum-mechanical effects for thin cylindrical Si-Nanowire MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Cousin, B. Rozeau, O. Jaud, M.-A. Jomaah, J.
Copyright Year	2009
Description	Author affiliation: IMEP, MINATEC, INPG, 3 Parvis Louis Néel, BP257, 38016 Grenoble, France (Jomaah, J.) \|\| CEA, LETI, MINATEC, F38054 Grenoble, France (Cousin, B.; Rozeau, O.; Jaud, M.-A.)
Abstract	Since we know that quantum-mechanical effects are predominant in surrounding-gate MOSFETs, a model should be developed. For the first time, this paper presents an analytic model of quantization for thin cylindrical Si-Nanowire MOSFETs by using a variational approach. The model is implemented into a surface potential like model. It is shown that results agree with the numerical simulations.
Starting Page	107
Ending Page	108
File Size	238795
Page Count	2
File Format	PDF
ISBN	9781424427840
ISSN	1930885X
DOI	10.1109/VTSA.2009.5159313
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-04-27
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Decision support systems Quadratic programming Virtual reality
Content Type	Text
Resource Type	Article

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