NDLI: Super-halo asymmetric vertical pass transistor design for ultra-dense DRAM technologies

Content Provider	IEEE Xplore Digital Library
Author	Chidambarrao, D. McStay, K. Weybright, M. Mandelman, J. Beintner, J. Li, Y. Crabbe, E.
Copyright Year	2003
Description	Author affiliation: IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA (Chidambarrao, D.)
Abstract	Device design of the super-halo asymmetric vertical pass transistor embedded in a cost-efficient, litho-friendly 8F/sup 2/ DRAM cell is described. This device not only retains the double-gate feature that provides twice the drive current, but also improves write-back performance critical for DRAM applications while meeting the stringent 1 fA off-current requirement. The key to achieving this degree of optimization is a super-halo angled Vt implant that produces multi-dimensionally graded well doping. The lateral grading provides small body effect and superior write-back performance that facilitates scaling with low wordline swings. The vertical grading leads to reduced short channel effect and de-coupled channel and node doping that not only reduces junction leakage but also allows aggressive scaling of the vertical device channel length.
Starting Page	25
Ending Page	28
File Size	206711
Page Count	4
File Format	PDF
ISBN	0780377656
ISSN	1524766X
DOI	10.1109/VTSA.2003.1252542
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-06
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Implants Doping Microelectronics Educational institutions Boron Planar arrays
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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