NDLI: 2.5 /spl Omega///spl square/ W/TiN/poly stack gate technology for high density and embedded DRAM technology

Content Provider	IEEE Xplore Digital Library
Author	Hu, Y. Anderson, D. Rotondaro, A. Obrien, S. Wei-Yung Hsu Kraft, R. Tiner, P. Nicollian, P. Aur, S.
Copyright Year	1999
Description	Author affiliation: Silicon Technol. Dev. Center, Texas Instrum. Inc., Dallas, TX, USA (Hu, Y.)
Abstract	A W/TiN/Poly gate stack has been developed and extensively characterized, and it is applied to a 0.2 /spl mu/m CMOS transistor design for Gigabit and embedded DRAM technology. The gate sheet is less than 2.5 /spl Omega///spl square/ with a 600 /spl Aring//200 /spl Aring//900 /spl Aring/ W/TiN/Poly gate stack at 0.16 /spl mu/m line width. The effective oxide thickness is found to be 3 /spl Aring/ thicker than a comparable poly-only gate. The oxide hard breakdown field can exceed 12 MV/cm and CHC lifetime is greater than 10 years with the W/TiN/Poly gate stack technology. In addition, a drive current of 400 /spl mu/A//spl mu/m for nMOS and 190 /spl mu/A//spl mu/m for pMOS have been achieved at 1 pA//spl mu/m off-current and 1.8 V Vcc with 5 nm gate oxide. This is the highest drive current reported to date for similar technologies.
Starting Page	247
Ending Page	250
File Size	249494
Page Count	4
File Format	PDF
ISBN	0780356209
DOI	10.1109/VTSA.1999.786046
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-06-10
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tin Random access memory Implants MOS devices Logic circuits Energy consumption Doping CMOS technology Threshold voltage Hot carriers
Content Type	Text
Resource Type	Article

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