NDLI: Universal Mobility-Field Curves for Electrons and Holes in MOS Inversion Layers

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Foreword: Welcome to Karuizawa, Japan for the Seventh Symposium on VLSI Technology

1987 VLSI Symposium Committee

0.5 μm Device Processing with Excimer Laser-Based Lithography

Advanced Excimer Laser Lithography

The Mechanism of the DESIRE Process

A Silicon-Added Bilayer Resist (SABRE) Process for High-Resolution Optical Lithography

Double Diffraction Alignment Method Using Checker Grating

Variable Proximity Corrections for Submicron Optical Lithographic Masks

Three Dimensional Process Simulator for Photo and Electron Beam Lithography, and Estimations of Proximity Effects

A Trench Isolation Technology for High-Speed and Low-Power Dissipation Bipolar LSI's

Field Isolation Process for Submicron CMOS

In-Situ MOS Gate Engineering in a Novel Rapid Thermal/Plasma Multiprocessing Reactor

Accelerated Testing of Silicon Dioxide Wearout

Very Thin Nitride/Oxide Composite Gate Insulator for VLSI CMOS

Photo Cleaning of Si Surface after Reactive Ion Etching

Analysis and Solution of a Yield-Limiting Patterned-Fail Mechanism in a 1 Mbit DRAM

A 100nm Emitter Transistor Fabricated with Direct EB Writing for High-Speed Bipolar LSIs

Reduced Process Sensitivity of Polysilicon Emitter Contacts for VLSI Bipolar Transistors

Thin-Base Bipolar Technology by Low-Temperature Photo-Epitaxy

Soft-Error Immune Switched-Load-Resistor Memory Cell

A 7GHz PnP Transistor for Complementary Bipolar LSI

Advanced One Micron BICMOS Technology for High Speed 256K SRAMS

Discontinuities in Very High-Speed Lossy Transmission Lines for Chip-to-Chip Interconnections

Hot-Carrier-Induced MOSFET Degradation: AC Versus DC Stressing

Hot-Carrier Degradation Mechanism under AC Stress in MOSFET's

Hot-Carrier Effects under Pulsed Stress in CMOS Devices

Unified Model for Electric Fields in LDD-Type MOSFETs

Mechanism of Hot-Electron-Induced NMOSFET's Degradation

Relationship between Gate Bias and Hot-Carrier Induced Instabilities in P-Channel MOSFETs

Sub Micron P-MOSFETs under Static and SWAP Stress

Ion-Enhanced Evaporated Tungsten for VLSI Applications

Submicron Tungsten Gate MOSFET with 10 nm Gate Oxide

Improvement of Dielectric Strength of Tisix-Polycide-Gate System by Using Rapidly Nitrided Oxides

Effects of Titanium Salicide Process on Oxide Charge Trapping and Hot-Electron Reliability in Submicron MOS Devices for VLSI

The Use of Cosi2 as Compared to Tisi2 for a Self-Aligned Silicide Technology

A High Aspect Ratio and High Throughput Sio2 Planarization Technology with Bias-ECR Plasma Deposition

Submicron Gap Planarization with Photo CVD and Spin-on-Glass Multi-Layers for Multi-Level Interconnections

A Novel Contact-Hole Filling Technology with Selective CVD-W for Shallow Junctions

Low-Resistive and Selective Silicon Growth as a Self-Aligned Contact Hole Filler and Its Application to 1m Bit Static RAM

PASPAC (Planaraized Al/Silicide/Poly Si with Self Aligned Contact) with Low Contact Resistance and High Reliability in CMOS LSIs

Hot Electron Energy Analysis Using a High-Speed Monte Carlo Simulation

Universal Mobility-Field Curves for Electrons and Holes in MOS Inversion Layers

Verification of an Analytic Model for Latchup in Epitaxial CMOS

Fllcker Noise in CMOS: A Unified Model for VLSI Processes

Technology and Modeling of Submicron Contacts

Formation of Si-on-Insulator Structure by Lateral Solid Phase Epitaxial Growth with Local P-Doping

Subquarter-Micrometer P-Channel MOSFET's with 80 Nm S/D Junctions

A High Density 4Mbit DRAM Process Using a Fully Overlapping Bitline Contact (FOBIC) Trench Cell

Trench Capacitor Using R.T.O. for Mega Bit DRAM's

A Band-to-Band Tunneling Effect in the Trench Transistor Cell

Experimental characterization of α-induced charge collection mechanism for megabit DRAM cells

A Folded Resistor and Capacitor (FRC) Static Memory Cell with Triple Poly-Si Structures

A New CMOS SRAM Cell with Fully Planarizing Technology

Shallow Trench Isolated Buried N+ FAMOS Transistors for VLSI EPROMs

A CMOS A/D Converter on Laser Recrystallized SOI with Controlling the Crystal Growth Direction

0.5μm CMOS Technology for 5.6nsec High Speed 16x16 Bit Multiplier

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

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1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

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