NDLI: Discrete Dopant Fluctuated 20nm/15nm-Gate Planar CMOS

Content Provider	IEEE Xplore Digital Library
Author	Fu-Liang Yang Jiunn-Ren Hwang Hung-Ming Chen Jeng-Jung Shen Shao-Ming Yu Yiming Li Tang, D.D.
Copyright Year	2007
Description	Author affiliation: Taiwan Semicond. Manuf. Co., Hsinchu (Fu-Liang Yang; Jiunn-Ren Hwang; Hung-Ming Chen; Jeng-Jung Shen)
Abstract	We have, for the first time, experimentally quantified random dopant distribution (RDD) induced V, standard deviation up to 40 mV for 20 nm-gate planar CMOS. Discrete dopants have been statistically positioned in the 3D channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". As gate length further scaling down to 15 nm, the newly developed discrete-dopant scheme features an effective solution to suppress 3-sigma-edge single digit dopants induced V, variation by gate work function modulation. The extensive study may postpone the scaling limit projected for planar CMOS.
Starting Page	208
Ending Page	209
File Size	3177863
Page Count	2
File Format	PDF
ISBN	9784900784031
DOI	10.1109/VLSIT.2007.4339695
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	JSAP
Subject Keyword	Doping Fluctuations Semiconductor process modeling Data mining Transistors Poisson equations Computational modeling Electrostatics Cities and towns Semiconductor device modeling
Content Type	Text
Resource Type	Article

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