NDLI: High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide

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Digital consumer electronics evolution in the multimedia and network age

The silicon opportunity of the new millenium-digital information appliances

High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme

A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SADD) process for 0.15 /spl mu/m stand-alone and embedded DRAMs

A 0.22 /spl mu/m CMOS-SOI technology with a Cu BEOL

A low voltage erase technique for DINOR flash memory devices

A novel high performance and reliability p-type floating gate n-channel flash EEPROM

A 0.9 V operation 2-transistor flash memory for embedded logic LSIs

Suppression of anomalous leakage current in tunnel oxides by fluorine implantation to realize highly reliable flash memory

0.18 /spl mu/m metal gate fully-depleted SOI MOSFETs for advanced CMOS applications

Minimizing body instability in deep sub-micron SOI MOSFETs for sub-1 V RF applications

SON (silicon on nothing)-a new device architecture for the ULSI era

High performance fully and partially depleted poly-Si surrounding gate transistors

A DRAM technology using MIM BST capacitor for 0.15 /spl mu/m DRAM generation and beyond

Aluminum word line and bit line fabrication technology for COB DRAM using a polysilicon-aluminum substitute

A new process integration-P/sup 3/ (pre poly plug)-for giga bit DRAM era

Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM

A novel clustered hard mask technology for dual damascene multilevel interconnects with self-aligned via formation using an organic low k dielectric

Slotted vias for dual damascene interconnects in 1 Gb DRAMs

High performance Cu interconnects with low-k BCB-polymers by plasma-enhanced monomer-vapor polymerization (PE-MVP) method

Low-k SiN film for Cu interconnects integration fabricated by ultra low temperature thermal CVD

Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs

A source/drain formation technology utilizing sub-10 keV arsenic and assist-phosphorus implantation for 0.13 /spl mu/m MOSFET

Improvement of CoSi/sub 2/ stability on fine grain sized poly-Si using nitrogen implantation through Co monosilicide and its effect on 0.18 /spl mu/m dual gate CMOS

Low resistance Co-salicided 0.1 /spl mu/m CMOS technology using selective Si growth

A concept of gate oxide lifetime limited by "B-mode" stress induced leakage currents in direct tunneling regime

Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability

Dielectric breakdown mechanism of thin-SiO/sub 2/ studied by the post-breakdown resistance statistics

C-V and gate tunneling current characterization of ultra-thin gate oxide MOS (t/sub ox/=1.3-1.8 nm)

An efficient lateral channel profiling of poly-SiGe-gated PMOSFET's for 0.1 /spl mu/m CMOS low-voltage applications

Indium tilted channel implantation technology for 60 nm nMOSFET

Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS

Channel engineering for 0.2 /spl mu/m surface channel pMOSFETs using electron beam irradiation

The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling

Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress

Quantum effect in oxide thickness determination from capacitance measurement

100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

Alpha-SER modeling and simulation for sub-0.25 /spl mu/m CMOS technology

Substrate enhanced gate current: device design and temperature impact and disturbs in programming flash memories with negative body bias

Novel bi-directional tunneling NOR (BiNOR) type 3-D flash memory cell

A self-aligned split-gate flash EEPROM cell with 3-D pillar structure

65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2 nm-thick gate oxide for 1.5 V operation

Smart pockets-total suppression of roll-off and roll-up [MOSFET doping]

0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)

Work function controlled metal gate electrode on ultrathin gate insulators

Inner cylinder Ta/sub 2/O/sub 5/ capacitor process for 1 Gb DRAM and beyond

Leakage-current mechanism of a tantalum-pentoxide capacitor on rugged Si with a CVD-TiN plate electrode for high-density DRAMs

In-situ multi-step (IMS) CVD process of (Ba,Sr)TiO/sub 3/ using hot wall batch type reactor for DRAM capacitor dielectrics

A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond

A 0.18 /spl mu/m high-performance logic technology

A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

Realization of 0.1 /spl mu/m buried-channel PMOSFETs by device restructuring using tilted well implantation technology

Integration of 3 level air gap interconnect for sub-quarter micron CMOS

R-1 technology challenges for scaled Cu/low k interconnects

R-2 gate insulator;Hi-k vs. SiO/sub 2/

R-3 flush vs. FeRAM which is the real winner?

SOI: what are the roadblocks, if any, to become a mainstream technology? (technology and circuits joint rump session)

High-integrity ultra-thin silicon nitride film grown at low temperature for extending scaling limit of gate dielectric

High performance and highly reliable deep submicron CMOSFETs using nitrided-oxide

Improvement of 1/f noise by using VHP (vertical high pressure) oxynitride gate insulator for deep-sub micron RF and analog CMOS

New optimization guidelines for sub-0.1 /spl mu/m CMOS technologies with 2 nm NO gate oxynitrides

Node connection/quantum phase-shifting mask-path to below 0.3-/spl mu/m pitch, proximity effect free random interconnect and memory patterning

New radical injection method for high-performance and chargeless dielectric etching

Balanced electron drift oxide etcher with Xe added gas chemistry for low cost and high performance contact metallization

Re-distribution of Cu contamination in advanced high-speed CMOS and its influence on device characteristics

A reliable 0.1 /spl mu/m Ta/sub 2/O/sub 5/ transistor manufactured with an almost standard CMOS process

Sub-quarter micron CMOS process for TiN-gate MOSFETs with TiO/sub 2/ gate dielectric formed by titanium oxidation

Device and reliability of high-k Al/sub 2/O/sub 3/ gate dielectric with good mobility and low D/sub it/

Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N/sub 2/O oxidation of NH/sub 3/-nitrided Si

Fully functional 0.5-/spl mu/m 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique

A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Al-interconnect/Cu-plug structure for FeRAM multilevel interconnect

A new 1T/2C merged two-terminal gain cell with SBT encapsulated floating gate MOSFET for highly scalable FeRAM

Transistor design issues in integrating analog functions with high performance digital CMOS

A 0.15-/spl mu/m/73-GHz f/sub max/ RF BiCMOS technology using cobalt silicide ring extrinsic-base structure

Submicron CMOS thermal noise modeling from an RF perspective

RF noise simulation for submicron MOSFET's based on hydrodynamic model

New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

Low-temperature metal/ON/HSG-cylinder capacitor process for high density embedded DRAMs

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

Enabling shallow trench isolation for 0.1 /spl mu/m technologies and beyond

Future perspective and scaling down roadmap for RF CMOS

Compact distributed RLC models for multilevel interconnect networks

Micro IDDQ test using Lorentz force MOSFET's

Monte Carlo modeling of threshold variation due to dopant fluctuations

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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