NDLI: Floorplan-based crosstalk estimation for macrocell-based designs

Content Provider	IEEE Xplore Digital Library
Author	Gupta, S. Katkoori, S. Sankaran, S.
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA (Gupta, S.; Katkoori, S.; Sankaran, S.)
Abstract	We propose an estimation technique to measure the crosstalk susceptibility of different nets in the post global routing phase, prior to detailed routing of designs. Global routing provides the approximate routes of the wires. This is used to compute the aggressors of a given victim wire along its route and its crosstalk susceptibility with respect to those aggressors. The crosstalk susceptibility of a victim wire is given by: (1) P/sub t/ the probability of crosstalk occurrence on the wire in different regions along its route; and (2) V/sub peak/ worst case noise amplitude experienced by the wire along its route. P/sub t/ is estimated using a very fast and accurate statistical estimator previously proposed by the authors. V/sub peak/ is estimated by predicting the cross-coupling capacitances between neighboring wires, using their global routing information. Placement and global routing are done using CADENCE silicon ensemble. The predicted crosstalk estimates are compared against those by detailed HSPICE simulations. Average errors are found to be less than 8% while the execution times are significantly reduced.
Starting Page	463
Ending Page	468
File Size	153319
Page Count	6
File Format	PDF
ISBN	0769522645
ISSN	10639667
DOI	10.1109/ICVD.2005.100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk Routing Wire Phase estimation Phase measurement Probability Noise level Capacitance Silicon Predictive models
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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