NDLI: Integrating self testability with design space exploration by a controller based estimation technique

Content Provider	IEEE Xplore Digital Library
Author	Gaur, M.S. Zwolinski, M.
Copyright Year	2004
Description	Author affiliation: Sch. of Electron. & Comput. Sci., Southampton Univ., UK (Gaur, M.S.; Zwolinski, M.)
Abstract	Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-Transfer-Level (RTL) data path generated from a behavioural description to make more testable. Although it can be argued that good results have been obtained-with such approaches, we must keep in mind that with the emergence of commercial behavioural synthesis tools it is difficult for the designer to understand an automatically generated structural RTL description. With the ever increasing complexity and pressure to shorten time to market, test synthesis must not be dissociated from design synthesis. This paper shows that it is possible to generate optimised self-testable RTL when addressed at the highest level of abstraction ie., behavioural description. This is achieved by developing a novel and accurate Built-in Self-Test (BIST) resource estimation technique based on exploitation of certain characteristics of the controller of the design.
Sponsorship	VLSI Soc. of India Minist. of Inf. and Commun. Technol., Gov. of India IEEE Electron Devices Soc. IEEE Circuits and Syst. Soc. Tata Consultancy Services Texas Instruments Inc. Nat. Semiconductor Intel Synopsys Cypress Semiconductor Corp. Infineon Technol. Cadence Conexant
Starting Page	901
Ending Page	906
File Size	347078
Page Count	6
File Format	PDF
ISBN	0769520723
DOI	10.1109/ICVD.2004.1261045
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-09
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Space exploration Electronic equipment testing Built-in self-test Very large scale integration Hardware design languages Scheduling Logic gates Consumer electronics Computer science
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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