NDLI: An Efficient Rule Based Fault Simulator

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A New Method for Generating Tests for Delay Faults in Non-Scan Circuits

A New Reliable Method for Delay-Fault Diagnosis

Functional Test Generation for Sequential Circuits

Minimizing Total Wire Length By Flipping Modules

An Effective Timing-Driven Placement Algorithm For Macro Cells

The k-layer Topological Via Minimization Problem on a Circular Channel

A Switch-Level Test Generation System

On Computing Tests for Bridging and Leakage Faults: Complexity Results and Universal Test Sets

On Bridging Faults in ECL Circuits

Single Phase Dynamic CMOS POS PLA

Design Migration Across Technology - Making It Work

Analysis of Design Methodology with Logic Cell Arrays

Concurrent Two-Dimensional State Minimization and State Assignment of finite State Machines

Interconnect Optimization Techniques in Data Path Synthesis

Towards System level modeling and synthesis

Optimization Techniques for Pipelined Scheduling

System Level Specification and Synthesis

Solving Physical Design Problems on a Vector Machine

OPSYN - OASYS Based Pseudosynthesis Tool

Mirroring Silicon Behaviour in ASIC models- The Issues Involved

Design And Fabrication Of GaAs 2-input Nor Gate

A Novel Scheme for Designing Error Correcting Codes Using Cellular Automata

A Behavioral Fault Simulator For Ideal

An Architecture To Test Random Access Memories

3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set

An Efficient Rule Based Fault Simulator

A Low-Cost High-Capacity Associative Memory Design Using Cellular Automata

Scalable, Pipelined, Cmos VLSI Content Addressable Memory Chips - Architecture And Implementation

An Array Architecture for Computing KLT Basis Vectors

Design and Implementation of High Speed RNS Input-Output Converters

Estimating the Complexity of Synthesized Designs from FSM Specifications

A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas

Combined Synthesis of Easily Testable Datapath and Control Designs

Synthesis of Self-Testable Sequential Logic Using Programmable Cellular Automata

An Efficient State Assignment Technique using Least Commitment and Constraint Propagation Techniques

Low Power Techniques for Portable Real-time DSP Applications

A CMOS VLSI Chip for Motion Detection

A Two-dimensional Systolic Array Processor for Image Processing

ECube: An Efficient Architecture for Analyzing Time-Varying Spectra

A Global Test Point Placement Algorithm of Combinational Circuits

Computational Complexity of Test-Point Insertions and Decompositions

A New Variable Testability Measure: a Concept for Data-Flow Testability Evaluation

An Efficient Method for Computation of Signatures

A Force Directed Hill-Climbing Placement Algorithm

An Algorithm for M Shortest Routes for a Net

An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing

N2S: An Automatic Netlist to Schematic generator

Constrained Via Minimisation In Greedy Channel Routing

Minimum Partition for the Space Region of VLSI Layout

CPM Pole-Zero Computation Using The Generalized Eigenproblem Approach

A New Accurate and Efficient Timing Simulator

Stepsize Control in Piecewise Approximate Circuit Simulation

Design of an Efficient ASIC for the Control of Microwave Ovens

WCS - A CAD Solution for Worst Case Performance Analysis of Integrated Circuits

Use of CMOS Technology in Wave Pipelining

Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC

A Designer's Perspective on VLSI Tools and Methodology

A System for Behavior Extraction from FPGA Implementations of Synchronous Designs

Data Path Synthesis With Global Time Constraint

From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits

Logic Design and Synthesis with IEEE Logic Symbols in the DEMET System

An ASIC for High Performance Stepper Motor Control

EPLDs - a Milestone in the World of Logic Design

Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low Temperature

Using Dedicated Functional Simulator for ASIC Design in Indian Context

A Simple Model for Lindhard Continuum Potential useful for Channeling Simulation

Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis

A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design Tasks

The "G-F" 2-Valued Formula Generating Complete Set of Tests to Multiple Faults

Quasi-Linear FSMS and their Application to the Generation of Deterministic and Pseudo-random Test Vectors

A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test

An Efficient Method For Characterization Of ASIC Compilers

Quad Asynchronous Communication Element (ACE) with FIFO

Benchmarking Array Comparators

Systolic Arithmetic Architectures

Design Considerations for a Flat Panel Controller

A New algorithm for combined PLA folding

Using a Balanced Quad List Quad Tree to Speed Up a Hierarchical VLSI Compaction Scheme

DEFLAN- A delay estimator for floorplanner

Structured Construction of VLSI Circuits Using Adjacency Lists

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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