NDLI: 8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction

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2015 Symposium on VLSI Circuits (VLSI Circuits)

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2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

IMT-2000 terminal and its requirements for device technologies

Micromachined microsystems: miniaturization beyond microelectronics

A monolithic surface micromachined Z-axis gyroscope with digital output

8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction

A low power, low noise, ultra-wide dynamic range CMOS imager with pixel-parallel A/D conversion

A CMOS image sensor for focal-plane low-power motion vector estimation

A wide-band direct conversion receiver with on-chip A/D converters

A 5.2-GHz CMOS receiver with 62-dB image rejection

A 2 GHz CMOS double conversion downconverter with robust image rejection performance against the process and temperature variations

A single-chip 2.4 GHz direct-conversion CMOS receiver for wireless local loop using one-third frequency local oscillator

A CMOS 50% duty cycle repeater using complementary phase blending

A low jitter dual loop DLL using multiple VCDLs with a duty cycle corrector

On-chip picosecond time measurement

A common-gate switched, 0.9 W class-E power amplifier with 41% PAE in 0.25 /spl mu/m CMOS

A translinear-based chip for linear LINC transmitters

A SOI-BiCMOS RF-transmitter for personal digital cellular communication (PDC)

A Si 2-GHz 5-bit LO-phase-shifting downconverter for adaptive antennas

A bit-line leakage compensation scheme for low-voltage SRAM's

A 1.8 V 18 Mb DDR CMOS SRAM with power reduction techniques

A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit

A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

Addressing ESD for microprocessors and ASICs in 21st century technologies

Where does memory go in the 21C? (Evolution and revolution of memory technology)

A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA

Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS

A 25.9-GHz voltage-controlled oscillator fabricated in a CMOS process

Analysis and design of silicon bipolar distributed oscillators

A next generation channeled-DRAM architecture with direct background-operation and delayed channel-replacement techniques

A 2.5 V, 20 Gbyte/s 288 M packet-based DRAM with enhanced cell efficiency and noise immunity

A DDR/SDR-compatible SDRAM design with a three-size flexible column redundancy

CMOS-logic-circuit-compatible DRAM circuit designs for wide-voltage and wide-temperature-range applications

Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers

1.6 Gb/s/pin 4-PAM signaling and circuits for a multi-drop bus

Sub-picosecond jitter SiGe BiCMOS transmit and receive PLLs for 12.5 Gbaud serial data communication

A 10-Gb/s CMOS clock and data recovery circuit

A 50-mW 14-bit 2.5-MS/s /spl Sigma/-/spl Delta/ modulator in a 0.25 /spl mu/m digital CMOS technology

Linearization method for fast voltage-to-current converters

A variable gain CMOS amplifier with exponential gain control

A new model for thermal channel noise of deep submicron MOSFETs and its application in RF-CMOS design

A dual page programming scheme for high-speed multi-Gb-scale NAND flash memories

1.25 volt, low cost, embedded flash memory for low density applications

A 60 ns access 32 kByte 3-transistor flash for low power embedded applications

A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories

A Si BiCMOS trans-impedance amplifier for 10 Gb SONET receiver

A 156 Mbps CMOS laser diode driver for optical burst-mode transmission

A constant slew-rate Ethernet line driver

Analog front end IC for category I and II ADSL

A clock distribution network for microprocessors

Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP)

470 ps 64-bit parallel binary adder [for CPU chip]

1 GHz leading zero anticipator using independent sign-bit determination logic

A low-power adiabatic driver system for AMLCDs

Level converters with high immunity to power-supply bouncing for high-speed sub-1-V LSIs

VLSI implementation of dynamically reconfigurable hardware-based cryptosystem

A 12 b 105 Msample/s, 850 mW analog to digital converter

An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

A 200 MHz, 3 mW, 16-tap mixed-signal FIR filter

An adaptive analog noise-predictive decision-feedback equalizer

A 1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache

A 2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 /spl mu/m CMOS bulk technology

The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies

A 16 GB/s, 0.18 /spl mu/m cache tile for integrated L2 caches from 256 KB to 2 MB

A 2-V 1.8-GHz fully-integrated CMOS dual-loop frequency synthesizer

A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

A very low power channel select filter for IS-95 CDMA receiver with on-chip tuning

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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Symposium 1988 on VLSI Circuits

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in