NDLI: Self-adjusting Bit-precision For Low-power Digital Filters

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2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

2013 Symposium on VLSI Circuits

2012 Symposium on VLSI Circuits (VLSIC)

2011 Symposium on VLSI Circuits - Digest of Technical Papers

2010 Symposium on VLSI Circuits

2009 Symposium on VLSI Circuits

2008 IEEE Symposium on VLSI Circuits

2007 IEEE Symposium on VLSI Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1997 Simposium On VLSI Circuits Digest Of Technical Papers [front matter and table of contents]

Evolution Of DVD By Advanced Semiconductor Technology

Fifty Years Of The Transistor : The Beginning Of Silicon Technology

The Design Of 300MIPS Microprocessor With A Full Associative TLB For Hand-held PC OS

Issue Logic For A 600 MHz Out-of-order Execution

A CMOS Temperature Sensor For PowerPC RISC Microprocessors

A 4.5 Megabit, 560MHz, 4.5 Gbyte/s High Bandwidth SRAM

A Delta-sigma Pulse Width Modulator With Pulse Dithering

1.2-v, 16-bit Audio A/d Converter With Suppressed Latch Error Noise

CMOS Charge-transfer Preamplifier For Offset-fluctuation In Low-power, High-accuracy Comparators

An 8-GSa/s 8-bit ADC System

Self-powered Low Power Signal Processing

A 32 X 32-bit Adiabatic Register File With Supply Clock Generator

Active Body-bias SOI-CMOS Driver Circuits

Pass-transistor/CMOS Collaborated Logic: The Best Of Both Worlds

High Speed Low EMI Digital Video Interface With Cable Deskewing and transition Minimization Coding

A Multi-mode Digital Detector Readout For Solid-state Medical Imaging Detectors

A Macroscopic Substrate Noise Model For Full Chip Mixed-signal Design Verification

High Speed Adder Circuit Using Dummy Carry method

A 500 MHz 32-word X 64-bit 8-port Self-resetting CMOS Register File And Associated Dynamic-to-static Latch

Precharged Cache Hit Logic With Flexible Timing Control

R-1 1 Gigahertz And Beyond - PLL And Clock Distribution

R-2 Competing Architectures And Cell Technologies For High Performance DRAMs

R-3 Will The Single-chip Rf Transceiver Dominate In The Range Of 1 To 2 GHz?

Technology And Circuits Joint Rump Session

Technology Innovations In Mobile Computers

Designing High Performance Microprocessors

An Embedded DRAM-FPGA Chip With Instantaneous Logic Reconfiguration

A Pixel-parallel Image Processor Using Logic Pitch-matched To Dynamic Memory

An Access-sequence Control Scheme To Enhance Random Access Performance Of Embedded DRAMs

Floating-well Charge Pump Circuits For Sub-2.0V Single Power Supply Flash Memories

Circuit Technologies For A Single-1.8V Flash Memory

A 3.4-Mbyte/sec Progra Mming 3-level NANDFlash Memory Saving 40% Die Size Per Bit

A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories

A 2.4-Gb/s CMOS clock recovering 1:8 demultiplexer

A 0.6/spl mu/m CMOS 4Gb/s Transceiver With Data Recovery Using Oversampling

An 11.8-Ghz 31-mW CMOS Frequency Divider

A Phase Interpolation Direct Digital Synthesizer With A Digitally Controlled Delay Generator

A Charge Tramfer Amplifier And Am Encoded Bus Aditectum For Low Power SRAM

A Hierarchical Sensing Scheme (HSS) Of High-density And Low-voltage Operation SRAMs

Low Supply Voltage CMOS Charge Pumps

High-density chain ferroelectric random-access memory (CFRAM)

On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's

A 2.7 Volt CMOS Broadband Low Noise Amplifier

A Very Low Offset 1.9-GHz Si Mixer For Direct Conversion Receivers

A 2V 1.9GHz Si Down-mixer With LC Phase Shifter

A Linearization Technique For CMOS RF Power Amplifiers

A Lean-power Gigascale LSI Using Hierarchical V/sub bb/ Routing Scheme With Frequency Adaptive V/sub t/ CMOS

A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction

A Lean Power Management technique: the lowest power consumption for the given operating speed of LSIs

A Data-transition Look-ahead DFF Circuit For Statistical Reduction In Power Consumption

A 1Gbit SDRAM With An Independent Sub-array Controlled Scheme And A Hierarchical Decoding Scheme

400MHz Random Column Operating Sdram Techniques With Self Skew Compensation

All-digital Multi-phase Delay Locked Loop For Internal Timing Generation In Embedded And/or High-speed DRAMs

A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme

A 950MHz Second-order Integrated LC Bandpass /spl alpha/spl sigma/ Modulator

A 900-MHz CMOS Direct Conversion Receiver

A CMOS Implementation Of CDMA/FM IF Signal Processor

A 75mW 128 MHz DS-CDMA Baseband Correlator For High-speed Wireless Applications

Dynamic Dielectric Protection For I/0 Circuits Fabricated In A 2.5V CMOS Technology Interfacing To A 3.3V LVTTL Bus

1 Gb/s Current-mode Bidirectional I/0 Buffer

Self-adjusting Bit-precision For Low-power Digital Filters

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Symposium 1989 on VLSI Circuits

Symposium 1988 on VLSI Circuits

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