NDLI: A low-power and wide tuning range frequency locked loop for a Cognitive Radio system

Content Provider	IEEE Xplore Digital Library
Author	Su Cui, Acharya, Venkatesh Banerjee, Bhaskar
Copyright Year	2009
Description	Author affiliation: Department of Electrical Engineering, University of Texas at Dallas, 800 W. Campbell Rd, Mailstop EC 33, Richardson, 75080, USA (Su Cui,; Acharya, Venkatesh; Banerjee, Bhaskar)
Abstract	We present a frequency locked loop with a novel frequency detector scheme that can be used in a phase locked loop for aided acquisition and reduces the locking time without increasing the loop bandwidth. This FLL scheme utilizes a novel frequency detector and negative-impedance converter acting as a current conveyor without using an op-amp. The clock is generated by a simple three stage ring voltage-controlled oscillator (VCO) and a reference clock is sensed by two frequency detectors and converted to currents that are proportional to the frequency. These two currents adjust the supply voltage of the VCO. It shows a good tuning linearity over the range of 200 MHz – 600 MHz with a maximum power consumption of 1.72mW at 1GHz in TSMC 0.18 μm standard CMOS Technology. The settling time of the FLL is 105 ns. The FLL can be used to develop multi-standard frequency synthesizers for cognitive radio applications.
Starting Page	364
Ending Page	367
File Size	74014
Page Count	4
File Format	PDF
ISBN	9781424426980
DOI	10.1109/RWS.2009.4957356
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tuning Frequency locked loops Cognitive radio Frequency conversion Voltage-controlled oscillators Clocks CMOS technology Phase detection Phase frequency detector Phase locked loops voltage controlled oscillator frequency locked loop negative impedance converter phase locked loop
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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