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Fifteenth International Symposium on Quality Electronic Design

International Symposium on Quality Electronic Design (ISQED)

Thirteenth International Symposium on Quality Electronic Design (ISQED)

2011 12th International Symposium on Quality Electronic Design

2010 11th International Symposium on Quality Electronic Design (ISQED)

2009 10th International Symposium on Quality Electronic Design

9th International Symposium on Quality Electronic Design (isqed 2008)

8th International Symposium on Quality Electronic Design (ISQED'07)

7th International Symposium on Quality Electronic Design (ISQED'06)

Proceedings of the 2006 7th International Symposium on Quality Electronic Design

7th International Symposium on Quality Electronic Design - Title

7th International Symposium on Quality Electronic Design - Copyright

Technical Subcommittees

Steering/Advisory Committee

Conference at a glance

Tutorial 1: Emerging Technologies for VLSI Design

Tutorial II: Variability and Its Impact on Design

Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?

Modular service-oriented platform architecture - a key enabler to SoC design quality

Deep sub-100 nm Design Challenges

Successful IP Business Models

Variational interconnect delay metrics for statistical timing analysis

Statistically aware SRAM memory array design

Robust dynamic node low voltage swing domino logic with multiple threshold voltages

Constructing current-based gate models based on existing timing library

Efficient model update for general link-insertion networks

Using abstraction for efficient formal verification of pipelined processors with value prediction

EFSM manipulation to increase high-level ATPG effectiveness

A technique for estimating the difficulty of a formal verification problem

A formal verification method of scheduling in high-level synthesis

Fast incremental link insertion in clock networks for skew variability reduction

Clock distribution architectures: a comparative study

Post-layout gate sizing for interconnect delay and crosstalk noise optimization

Interconnect and thermal-aware floorplanning for 3D microprocessors

Simplicity and executability: cornerstones of quality

A compact DC and AC model for circuit simulation of high voltage VDMOS transistor

A complete carrier-based non-charge-sheet analytic theory for nano-scale undoped surrounding-gate MOSFETs

METS: a metric for electro-thermal sensitivity, and its application to FinFETs

A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

Improving transient error tolerance of digital VLSI circuits using robustness compiler (ROCO)

Probabilistic delay budgeting for soft realtime applications

TBNM - transistor-level boundary model for fast gate-level noise analysis of macro blocks

Fast sequential cell noise immunity characterization using meta-stable point of feedback loop

Pessimism reduction in static timing analysis using interdependent setup and hold times

Power islands: a high-level technique for counteracting leakage in deep sub-micron

Simultaneous statistical delay and slew optimization for interconnect pipelines

System-level SRAM yield enhancement

Sensing margin analysis of MLC flash memories using a novel unified statistical model

The statistics of device variations and its impact on SRAM bitcell performance, leakage and stability

A simulation-based soft error estimation methodology for computer systems

SRAM local bit line access failure analyses

Impact of NBTI on SRAM read stability and design for reliability

Minimizing FPGA reconfiguration data at logic level

Structure synthesis of analog and mixed-signal circuits using partition techniques

Language-based high level transaction extraction on on-chip buses

Clock skew scheduling under process variations

A CMOS thermal sensor and its applications in temperature adaptive design

Monte Carlo-alternative probabilistic simulations for analog systems

Critical path analysis considering temperature, power supply variations and temperature induced leakage

Process window and device variations evaluation using array-based characterization circuits

Novel decoupling capacitor designs for sub-90nm CMOS technology

Localized on-chip power delivery network optimization via sequence of linear programming

Non-physical pseudo-wave-based modal decoupling technique of multi-coupled coplanar transmission lines with homogeneous dielectric media

Enhancement of signal integrity and power integrity with embedded capacitors in high-speed packages

An improved AMG-based method for fast power grid analysis

Formal verification of pipelined microprocessors with delayed branches

Power-aware test pattern generation for improved concurrency at the core level

Advances in computation of the maximum of a set of random variables

A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology

Leakage biased sleep switch domino logic

Improvements to CBCM (charge-based capacitance measurement) for deep submicron CMOS technology

Design of a single event upset (SEU) mitigation technique for programmable devices

Area efficient temporal coding schemes for reducing crosstalk effects

Processing rate optimization by sequential system floorplanning

Fast Boolean matching with don't cares

A methodology for layout aware design and optimization of custom network-on-chip architectures

Core network interface architecture and latency constrained on-chip communication

Design space exploration of RTL datapaths using Rent parameter based stochastic wirelength estimation

Equivalence checking of C programs by locally performing symbolic simulation on dependence graphs

System-level process variability compensation on memory organizations of dynamic applications: a case study

A low input, low-power dissipation CMOS ADC

Constant impedance scaling paradigm for scaling LC transmission lines

Quasi-one-step Gauss-Jacobi method for large-scale interconnect analysis via RLCG-MNA formulation

Analysis of pulse signaling for low-power on-chip global bus design

Information theoretic capacity of long on-chip interconnects in the presence of crosstalk

Compact reduced order modeling for multiple-port interconnects

Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching

Reducing the data switching activity on serial link buses

Efficient multiphase test set embedding for scan-based testing

Evaluation of collapsing methods for fault diagnosis

On N-detect pattern set optimization

On optimizing scan testing power and routing cost in scan chain design

An improved method for identifying linear dependencies in path delay faults

Delay fault diagnosis for nonrobust test

Yield improvement by local wiring redundancy

Via distribution model for yield estimation

The use of the manufacturing sensitivity model forms to comprehend layout manufacturing robustness for use during device design

DFM metrics for standard cells

Yield enhancement methodology for CMOS standard cells

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Who is really responsible for quality throughout the design process?

Adding Manufacturability to the Quality of Results

Future Memory Technology Trends and Challenges

Device and Technology Challenges for Nanoscale CMOS

A totally self-checking S-box architecture for the advanced encryption standard

Jitter decomposition by time lag correlation

Design of window comparators for integrator-based capacitor array testing circuits

Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs

Exploring the ability of oscillation based test for testing continuous-time ladder filters

Data replication in banked DRAMs for reducing energy consumption

Parameterizable architecture-level SRAM power model using circuit-simulation backend for leakage calibration

Dual-K versus dual-T technique for gate leakage reduction: a comparative perspective

Compiler-directed power density reduction in NoC-based multicore designs

Shared scratch-pad memory space management

New generation of predictive technology model for sub-45nm design exploration

A non-volatile embedded memory for high temperature automotive and high-retention applications

Method to evaluate cable discharge event (CDE) reliability of integrated circuits in CMOS technology

Analysis of process variation's effect on SRAM's read stability

Logic SER reduction through flip flop redesign

Time redundancy based scan flip-flop reuse to reduce SER of combinational logic

Thermal trends in emerging technologies

Power gating with multiple sleep modes

SMM: scalable analysis of power delivery networks by stochastic moment matching

Accurate thermal analysis considering nonlinear thermal conductivity

Minimizing ohmic loss in future processor IR events

gmTest: an industry-wide database of VLSI layouts for quality control

ConvexSmooth: a simultaneous convex fitting and smoothing algorithm for convex optimization problems

A watermarking system for IP protection by buffer insertion technique

Partial selective encryption: an improved system for protecting VLSI design data in the OASIS format

Transistor-level optimization of supergates

Study of floating fill impact on interconnect capacitance

The challenges and impact of parasitic extraction at 65 nm

Pre-layout inductive corners for advanced digital design interconnect: modeling and silicon validation

A mixed boundary element method for extracting frequency-dependent inductances of 3D interconnects

LOTUS: leakage optimization under timing uncertainty for standard-cell designs

Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization

Low-leakage SRAM design with dual V/sub t/ transistors

Dual-Vt design of FPGAs for subthreshold leakage tolerance

Gate sizing and replication to minimize the effects of virtual ground parasitic resistances in MTCMOS designs

Impact of gate-length biasing on threshold-voltage selection

FASER: fast analysis of soft error susceptibility for cell-based designs

Diagnosis and design for diagnosability for Internet routers

Enabling quality and schedule predictability in SoC design using HandoffQC

Transaction level error susceptibility model for bus based SoC architectures

System-level design methodology with direct execution for multiprocessors on SoPC

Question: DRC or DfM? Answer: FMEA and ROI

Statistical analysis of capacitance coupling effects on delay and noise

Bringing manufacturing into design via process-dependent SPICE models

Stress-aware design methodology

A DFM methodology to evaluate the impact of lithography conditions on the speed of critical paths in a VLSI circuit

Participating Organizations

Best Paper Award

Call for Papers

Sixth international symposium on quality electronic design (isqed'05)

International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720)

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

Proceedings International Symposium on Quality Electronic Design

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)

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Sl.	Authority	Responsibilities	Communication Details
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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